參數(shù)資料
型號(hào): TMC3211
廠商: Fairchild Semiconductor Corporation
英文描述: 32-Bit, 20 MOPS Integer Divider(32位,20MOPS 整數(shù)除法器)
中文描述: 32位,20拖把整數(shù)分頻器(32位,20MOPS整數(shù)除法器)
文件頁(yè)數(shù): 4/10頁(yè)
文件大小: 90K
代理商: TMC3211
PRODUCT SPECIFICATION
TMC3211
4
REV. 1.0.1 5/9/00
Applications Discussion
Division Using A Constant
By utilizing the separate input data register load enable con-
trols, the TMC3211 can perform division by a constant. The
data currently held remain in the input registers until updated
by the user.
Data Formats
The TMC3211 supports fixed-point two’s complement data
formats. By keeping track of the binary points of the input
data, the user can then interpret the resulting quotient prop-
erly. Two possible binary weightings of the input and output
bits are as follows:
Figure 1. Integer Data Format
Figure 2. Fractional Data Format
Pin
D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Y
-2
31
2
30
2
29
2
28
2
27
2
26
2
25
2
24
2
23
2
22
2
21
2
20
2
19
2
18
2
17
2
16
2
15
2
14
2
13
2
12
2
11
2
10
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
X
-2
15
2
14
2
13
2
12
2
11
2
10
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
Q
-2
31
2
30
2
29
2
28
2
27
2
26
2
25
2
24
2
23
2
22
2
21
2
20
2
19
2
18
2
17
2
16
2
15
2
14
2
13
2
12
2
11
2
10
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
Y
-2
0
.2
-1
2
-2
2
-3
2
-4
2
-5
2
-6
2
-7
2
-8
2
-9
2
-10
2
-11
2
-12
2
-13
2
-14
2
-15
2
-16
2
-17
2
-18
2
-19
2
-20
2
-21
2
-22
2
-23
2
-24
2
-25
2
-26
2
-27
2
-28
2
-29
2
-30
2
-31
X
-2
0
.2
-1
2
-2
2
-3
2
-4
2
-5
2
-6
2
-7
2
-8
2
-9
2
-10
2
-11
2
-12
2
-13
2
-14
2
-15
Q
-2
15
.2
14
2
13
2
12
2
11
2
10
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
2
-1
2
-2
2
-3
2
-4
2
-5
2
-6
2
-7
2
-8
2
-9
2
-10
2
-11
2
-12
2
-13
2
-14
2
-15
2
-16
where a leading minus sign indicates a sign bit.
Care must be taken when adopting fractional data formats.
By observing the binary weighting applied to the input data
in the dividend and divisor, the binary point of the quotient
can then be correctly established. The difference lies only in
constant scale factors, which must be considered in order to
maintain a data format which is compatible with the bit
weighting of the hardware system. The two most common
choices are fractional and integer notation. If integer notation
is used, the LSBs of the dividend, divisor, and quotient all
have the same value. With fractional notation the MSBs are
all of equal weight.
Divide by Zero
The flag DZ indicates that the divisor input for the current
calculation was a zero, independent of the dividend. Dividing
by zero is an undefined operation yielding a meaningless
quotient. Thus, this flag must be monitored to guard against
possible errors.
Inexact Results
The flag REM is provided to indicate that the current quotient
left a nonzero remainder and was truncated toward zero.
Negative Full-Scale Overflow
Due to a finite data word width, a two’s complement over-
flow error occurs under the following unique condition:
Divisor Y=80000000
H
(– Full-Scale)
Dividend X=FFFF
H
(-1)
Result:
Quotient Q=80000000
H
(– Full-Scale)
As stated above, this is due to a limitation in the number of bits
available to indicate a positive full-scale quotient, and data
overflows into the MSB position to indicate an incorrect sign.
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