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參數(shù)資料
| 型號： | TMC3211 |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | 32-Bit, 20 MOPS Integer Divider(32位,20MOPS 整數(shù)除法器) |
| 中文描述： | 32位，20拖把整數(shù)分頻器（32位，20MOPS整數(shù)除法器） |
| 文件頁數(shù)： | 3/10頁 |
| 文件大?。?/td> | 90K |
| 代理商： | TMC3211 |
TMC3211
PRODUCT SPECIFICATION
REV. 1.0.1 5/9/00
3
Pin Descriptions
Signal
Type
Power
Signal
Name
V
DD
Pin Number
Description
B3, A4, A13, D11, F11, G12, J11,
K11, L11, L7, L4, L2, J3, G3, F3,
C2, C3
A1, C4, C11, C12, E11, H11, L12,
M12, M11, L5, L3, N1, K3, H3, G2,
E3, D3
M9
Supply Voltage, Ground.
a single +5V supply. All power and ground lines must
be connected.
The TMC3211 operates on
GND
Clock
CLK
System Clock.
All input and output signal timing is referenced to the
rising edge of Clock.
Dividend Data.
The 32-bit Dividend is presented
through the registered Y input port. Y
The LSB is Y
0
.
The TMC3211 has a single Clock input.
Inputs
Y
31-0
M1, L1, K2, K1, J2, J1, H2, H1, G1,
F1, F2, E1, E2, D1, D2, C1, B2, A2,
A3, B4, C5, B5, A5, C6, B6, A6, A7,
C7, B7, A8, B8, C8
U8, M8, N8, N7, M7, N6, M6, L6,
NS, MS, N4, M4, N3, M3, N2, M2
31
is the sign bit.
X
15-0
Divisor Data.
the registered X input port. X
is X
0
.
Quotient Data.
registered Q output bus. Q
is Q
0
.
The 16-bit Divisor is presented through
is the sign bit. The LSB
15
Outputs
Q
31-0
L9, M10, N11, N12, L10, N13, M13,
L13, K12, K13, J12, J13, H12, H13,
G11, G13, F13, F12, E13, E12,
D13, D12, C13, B13, B12, A12,
C10, B11, A11, B10, C9, A10
B1
The current Quotient is available on the
is the sign bit. The LSB
31
Controls
YEN
Dividend Write Enable.
input Y
31-0
is latched into the input registers on the
rising edge of clock when the enable control YEN is
LOW.
Divisor Write Enable.
Data present at the Divisor input
X
15-0
is latched into the input registers on the rising
edge of clock when the enable control XEN is LOW.
Quotient Output Enable.
The quotient output bus Q
and flags DZ and REM are in the high-impedance state
when the registered Output Enable OEQ is HIGH.
When OEQ is LOW, they are enabled on the next clock
cycle.
Divide-By Zero Flag.
When a zero divisor is input, the
resulting invalid output quotient will be accompanied by
a registered Divide-By-Zero Flag HIGH.
Inexact Remainder Flag.
Whenever a division
operation leaves a nonzero remainder, the resulting
qotient is accompanied by a registered nonzero
Remainder Flag HIGH.
Index Pin
(optional)
Data present at the Dividend
XEN
N9
OEQ
N10
31-0
Flags
DZ
B9
REM
A9
No
Connect
D4
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