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參數資料
| 型號： | TM4EP72CPN-70 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | EXTENDED-DATA-OUT DYNAMIC RAM MODULES |
| 中文描述： | 擴展數據輸出動態(tài)隨機存儲器模塊 |
| 文件頁數： | 7/22頁 |
| 文件大小： | 354K |
| 代理商： | TM4EP72CPN-70 |
TM4EP64BJN, TM4EP64BPN, TM4EP64CJN, TM4EP64CPN 4194304 BY 64-BIT
TM4EP72BJN, TM4EP72BPN, TM4EP72CJN, TM4EP72CPN 4194304 BY 72-BIT
EXTENDED-DATA-OUT DYNAMIC RAMMODULES
SMMS682A – AUGUST 1997– REVISED MARCH 1998
7
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
electrical characteristics over recommended ranges of supply voltage and ambient temperature
(unless otherwise noted)
TM4EP64BxN
PARAMETER
TEST CONDITIONS
’4EP64BxN-50
MIN
’4EP64BxN-60
MIN
’4EP64BxN-70
MIN
UNIT
MAX
MAX
MAX
VOH
High-level
output
voltage
IOH = – 2 mA
LVTTL
2.4
2.4
2.4
V
IOH = – 100
μ
A
LVCMOS
VDD–0.2
VDD–0.2
VDD–0.2
VOL
Low-level
output
voltage
IOL = 2 mA
LVTTL
0.4
0.4
0.4
V
IOL = 100
μ
A
LVCMOS
0.2
0.2
0.2
II
Input current
(leakage)
VDD = 3.6 V,
All others = 0 V to VDD
VI = 0 V to 3.9 V,
±
20
±
20
±
20
μ
A
IO
Output
current
(leakage)
VDD = 3.6 V,
CASx high
VO = 0 V to VDD,
±
20
±
20
±
20
μ
A
ICC1§
Average
read- or
write-cycle
current
VDD = 3.6 V,
Minimum cycle
1920
1600
1440
mA
ICC2
Average
standby
current
VIH = 2 V (LVTTL),
After one memory cycle,
RASx and CASx high
32
32
32
mA
VIH = VDD – 0.2 V (LVCMOS),
After one memory cycle,
RASx and CASx high
16
16
16
mA
ICC3§
Average
refresh
current
(RASx-only
refresh
or CBR)
VDD = 3.6 V,
RASx cycling,
CASx high (RASx-only refresh),
RASx low after CASx low (CBR)
Minimum cycle,
1920
1600
1440
mA
ICC4
Average
EDO current
VDD = 3.6 V,
RASx low,
tHPC = MIN,
CASx cycling
1760
1440
1280
mA
For conditions shown as MIN/MAX, use the appropriate value specified in the timing requirements.
Measured with outputs open
§Measured with a maximum of one address change while RASx = VIL
Measured with a maximum of one address change during each EDO cycle, tHPC
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