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參數(shù)資料
| 型號： | TC850ILW |
| 廠商： | Microchip Technology Inc. |
| 英文描述： | 15-Bit, Fast Integrating CMOS A/D Converter |
| 中文描述： | 15位，快速集成的CMOS A / D轉(zhuǎn)換 |
| 文件頁數(shù)： | 12/14頁 |
| 文件大小： | 164K |
| 代理商： | TC850ILW |
3-88
TELCOM SEMICONDUCTOR, INC.
15-BIT, FAST-INTEGRATING CMOS
ANALOG-TO-DIGITAL CONVERTER
TC850
Figure 7. Interface to Typical
μ
P Data Bus
ADDRESS
DECODE
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
CS
A2
.
L/H
OVR/POL
RD
WR
BUSY
CS
+5V
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
A15
A0
A1
RD
WR
INTERRUPT
ADDRESS
DATA BUS
CONT/DEMAND
μ
P
TC850
X00
X01
X10
HIGH BYTE AND POLARITY
LOW BYTE
HIGH BYTE AND OVERRANGE
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
BUSY
RD
PB0
CS
NC
CS
WR
+5V
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
INTERRUPT
CONT/DEMAND
μ
C OR
μ
P
I/O PORT
TC850
Figure 8. Interface to Typical
μ
P I/O Port or Single-Chip
μ
C
Since the PA0–PA7 inputs are dedicated to reading
A/D data, the A/D CS/CE inputs can be enabled continu-
ously. In continuous mode, data must be read in 3 bytes, as
shown in Table I. The required RD pulses are provided by a
μ
C/
μ
P output pin.
The circuit of Figure 8 can also operate in the demand
mode, with the start-up conversion strobe generated by a
μ
C/
μ
P output pin. In this case, the L/H and CONT/DEMAND
inputs can be controlled by I/O pins and the RD input
connected to digital ground.
Demand Mode Interface Timing
When CONT/DEMAND input is LOW, the TC850 per-
forms a conversion each time CE and CS are active and WR
is strobed LOW.
The demand mode conversion timing is shown in Figure
9. BUSY goes LOW and data is valid 1155 clock pulses after
WR goes LOW. After BUSY goes low, 125 additional clock
cycles are required before the next conversion cycle will
begin.
Once conversion is started, WR is ignored for 1100
internal clock cycles. After 1100 clock cycles, another WR
pulse is recognized and initiates a new conversion when the
present conversion is complete. A negative edge on WR is
required to begin conversion. If WR is held LOW, conver-
sions will not occur continuously.
The A/D conversion data is valid on the falling edge of
BUSY, and remains valid until one-half internal clock cycle
before BUSY goes HIGH on the succeeding conversion.
BUSY can be monitored with an I/O pin to determine end of
conversion, or to generate a
μ
P interrupt.
In demand mode, the three data bytes can be read in
any desired order. The TC850 is simply regarded as three
bytes of memory and accessed accordingly. The bus output
timing is shown in Figure 10.
Continuous Mode Interface Timing
When the CONT/DEMAND input is HIGH, the TC850
performs conversions continuously. Data will be valid on the
falling edge of BUSY, and all three bytes must be read within
443-1/2 internal clock cycles of BUSY going LOW. The
timing diagram is shown in Figure 11.
In continuous mode, OVR/POL and L/H byte-select
inputs are ignored. The TC850 automatically cycles through
three data bytes, as shown in Table I. Bus output timing in
the continuous mode is shown in Figure 12.
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| TC850 | 15-Bit, Fast Integrating CMOS A/D Converter |
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| TC850ILW | 15-BIT, FAST-INTEGRATING CMOS ANALOG-TO-DIGITAL CONVERTER |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TC850ILW713 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 16 Bit Hi Speed A/D RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| TC8521AM | 制造商:TOSHIBA 制造商全稱:Toshiba Semiconductor 功能描述:REAL TIME CLOCK ケ |
| TC8521AP | 制造商:TOSHIBA 制造商全稱:Toshiba Semiconductor 功能描述:REAL TIME CLOCK ケ |
| TC8566AF | 制造商:TOSHIBA 制造商全稱:Toshiba Semiconductor 功能描述:FLOPPY DISK CONTROLLER |
| TC8569AF | 制造商:TOSHIBA 制造商全稱:Toshiba Semiconductor 功能描述:FLOPPY DISK CONTROLLER |
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