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參數(shù)資料
| 型號： | TC3299A |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Ethernet PCMCIA Controller + COMBO Transceiver |
| 中文描述： | PCMCIA控制器組合以太網(wǎng)收發(fā)器 |
| 文件頁數(shù)： | 21/26頁 |
| 文件大小： | 1301K |
| 代理商： | TC3299A |
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TC3299A
Preliminary Data Sheet
Network Tally Counter Registers (CNTR)
Three 8-bit counters are provided for monitoring the number of CRC errors, Frame Alignment Errors and
missed packets, The maximum count reached by any counter is 192 (C0H). These registers will be
cleared when read by the CPU. The count is recorded in binary in CT0-CT7 of each Tally Register.
CNTR0: Monitor the number of Frame Alignment error
7
6
5
4
CT7
CT6
CT5
CT4
CNTR1: Monitor the number of CRC error
7
6
5
4
CT7
CT6
CT5
CT4
CNTR2: Monitor the number of Missed Packets
7
6
5
4
CT7
CT6
CT5
CT4
Number of Collisions Register (NCR)
This register contains the number of collisions a node experiences when attempting to transmit a packet.
If no collisions are experienced during a transmission attempt, the COL bit of the TSR will be set and the
contents of NCR will be zero. If there are excessive collisions, the ABT bit in the TSR will not be set and
the contents of NCR will be zero. The NCR is cleared after the TXP bit in the CR is set.
7
6
5
4
-
-
-
-
FIFO Register (FIFO)
This is an 8-bit register that allows the CPU to examine the contents of the FIFO after loopback. The FIFO
will contain the last 8 data bytes transmitted in the loopback packet. Sequential reads from the FIFO will
advance a pointer in the FIFO and allow reading of all 8 bytes. Note that the FIFO should only be read
when the EPCC has been programmed in loopback mode.
7
6
5
4
DB7
DB6
DB5
DB4
Physical Address Registers (PAR0-PAR5)
The physical address registers are used to compare the destination address of incoming packets for
rejecting or accepting packets. Comparisons are performed on a byte-wide basis. The bit assignment
shown below relates the sequence in PAR0-PAR5 to the bit sequence of the received packet.
..
Syn
Syn
DA0
DA1
DA2
|------- DestinationAddress --------|-- Source
D7
D6
D5
D4
PAR0
DA7
DA6
DA5
DA4
PAR1
DA15
DA14
DA13
DA12
PAR2
DA23
DA22
DA21
DA20
PAR3
DA31
DA30
DA29
DA28
PAR4
DA39
DA38
DA37
DA36
PAR5
DA47
DA46
DA45
DA44
3
2
1
0
CT3
CT2
CT1
CT0
3
2
1
0
CT3
CT2
CT1
CT0
3
2
1
0
CT3
CT2
CT1
CT0
3
2
1
0
NC3
NC2
NC1
NC0
3
2
1
0
DB3
DB2
DB1
DB0
DA3
DA4
DA5
DA6
DA7
..
D3
DA3
DA11
DA19
DA27
DA35
DA43
D2
DA2
DA10
DA18
DA26
DA34
DA42
D1
DA1
DA9
DA17
DA25
DA33
DA41
D0
DA0
DA8
DA16
DA24
DA32
DA40
Confidential.
Copyright
2003, IC Plus Corp.
21/26
August 27, 20003
TC3299A-DS-R30
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