參數(shù)資料
型號(hào): TC3299A
廠商: Electronic Theatre Controls, Inc.
英文描述: Ethernet PCMCIA Controller + COMBO Transceiver
中文描述: PCMCIA控制器組合以太網(wǎng)收發(fā)器
文件頁(yè)數(shù): 19/26頁(yè)
文件大?。?/td> 1301K
代理商: TC3299A
TC3299A
Preliminary Data Sheet
This register records status of the received packet, including information on errors and the type of
address match, either physical or multicast. The contents of this register are written to buffer memory by
the DMA after reception of a good packet. If packets with errors are to be saved the receive status is
written to memory at the head of the erroneous packet if an erroneous packet is received. If packets with
errors are to be rejected the RSR will not be written to memory. The contents will be cleared when the
next packet arrives. CRC errors, frame Alignment errors and missed packets are counted internally by the
EPCC which relinquishes the Host from reading the RSR in real time to record errors for Network
Management functions. The contents of this register are not specified until after the first reception.
7
6
5
4
DFR
DIS
PHY
MPA
Bit
Symbol
D0
PRX
Packet Received Intact: Indicates packet received without error. (Bits
CRC, FAE, FO and MPA are zero for the received packet.)
D1
CRC
CRC Error: Indicates packet received with CRC error. Increments Tally
Counter (CNTR1). This bit will also be set for Frame Alignment errors.
D2
FAE
Frame Alignment Error: Indicates that the incoming packet did not end on
a byte boundary and the CRC did not match at last byte boundary.
Increments Tally counter (CNTR0).
D3
FO
FIFO Overrun: This bit is set when the FIFO is not serviced causing
overflow during reception. Reception of the packet will be aborted.
D4
MPA
Missed Packet: Set when packet intended for node cannot be accepted
by EPCC because of a lack of receive buffers of if the controller is in
monitor mode and did not buffer the packet to memory. Increments Tally
Counter (CNTR2).
D5
PHY
Physical/Multicast Address: Indicates whether received packet had a
physical or multicast address type
0: Physical Address Match
1: Multicast/Broadcast Address Match
D6
DIS
Receiver Disabled: Set when receiver disabled by entering Monitor
mode. Reset when receiver is re-enabled when exiting Monitor mode.
D7
DFR
Deferring: Set when CRS or COL inputs are active. If the transceiver has
asserted the CD line as a result of the jabber, this bit will stay set
indicating the jabber condition.
3
2
1
0
FO
FAE
CRC
PRX
Description
Note: Following coding applies to CRC and FAE bits
FAE CRC Type of Error
0 0 No error (Good CRC and <6 Dribble Bits)
0 1 CRC ERROR
1 0 Legal, will not occur
1 1 Frame Alignment Error and CRC Error
Interrupt Mask Register (IMR)
The interrupt Mask Register is used to mask interrupts. Each interrupt mask bit corresponds to a bit in the
Interrupt Status Register (ISR). If an interrupt mask bit is set an interrupt will be issued whenever the
corresponding bit in the ISR is set. If any bit in the IMR is set low, an interrupt will not occur when the bit in
the ISR is set. The IMR powers up all zeroes.
7
6
5
4
-
RDCE
CNTE
OVWE
3
2
1
0
TXEE
RXEE
PTXE
PRXE
Confidential.
Copyright
2003, IC Plus Corp.
19/26
August 27, 20003
TC3299A-DS-R30
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