Precision Edge SY89536L Micrel, Inc. M9999-010808 hbwhelp@micrel.com or (408) 955-1690 Rate FSEL MSE" />
參數(shù)資料
型號: SY89536LHC
廠商: Micrel Inc
文件頁數(shù): 4/16頁
文件大小: 0K
描述: IC SYNTHESIZR LVPECL/HSTL 64TQFP
標(biāo)準(zhǔn)包裝: 160
系列: Precision Edge®
類型: 時(shí)鐘/頻率合成器
PLL: 帶旁路
輸入: CMOS,HSTL,LVDS,LVPECL,LVTTL,SSTL
輸出: HSTL,LVPECL
電路數(shù): 1
比率 - 輸入:輸出: 1:13
差分 - 輸入:輸出: 是/是
頻率 - 最大: 500MHz
除法器/乘法器: 是/無
電源電壓: 1.6 V ~ 3.6 V
工作溫度: 0°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-TQFP 裸露焊盤
供應(yīng)商設(shè)備封裝: 64-EP-TQFP
包裝: 托盤
12
Precision Edge
SY89536L
Micrel, Inc.
M9999-010808
hbwhelp@micrel.com or (408) 955-1690
Rate
FSEL
MSEL
REFCLK
Protocol
(MHz)
(Post Divider)
(Feedback Div.)
(MHz)
PSEL
FOUT
PCI
33
18
36
16.67
1
33
Fast Ethernet
100
6
40
15
1
100
1/8 FC
133
6
52
15.36
1
133
ESCON
200
4
50
16
1
200
SUGGESTED SELECTIONS FOR SPECIFIC CUSTOMER APPLICATIONS(Notes 1, 2, 3)
Note 1.
600MHz < (REFCLK
÷ PSEL × MSEL) < 1000MHz.
Note 2.
14MHz
≤ (REFCLK ÷ PSEL) ≤ 20MHz.
Note 3.
Where two settings provide the user with the identical desired frequency, the setting with the higher PLL input reference frequency (and lower
feedback divider) will usually have lower output jitter. However, the reference input frequency, as well as the VCO frequency, must be kept
within their respective ranges.
FOUT
REFCLK PSEL MSEL
FSEL
=
÷×
()
M3
M2
M1
M0
VCO Frequency(1)
0000
REFCLK
÷ PSEL × 34
0001
REFCLK
÷ PSEL × 36
0010
REFCLK
÷ PSEL × 38
0011
REFCLK
÷ PSEL × 40
0100
REFCLK
÷ PSEL × 42
0101
REFCLK
÷ PSEL × 44
0110
REFCLK
÷ PSEL × 48
0111
REFCLK
÷ PSEL × 50
1000
REFCLK
÷ PSEL × 52
1001
REFCLK
÷ PSEL × 54
1010
REFCLK
÷ PSEL × 56
1011
REFCLK
÷ PSEL × 60
1100
REFCLK
÷ PSEL × 62
1101
REFCLK
÷ PSEL × 66
1110
REFCLK
÷ PSEL × 30
1111
REFCLK
÷ PSEL × 32
FEEDBACK DIVIDE SELECT TABLE (MSEL)
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