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參數(shù)資料
| 型號(hào)： | STV2249 |
| 元件分類： | 參考電壓二極管 |
| 英文描述： | Low Current Operation at 250 ，Low Reverse Leakage,Low Noise Zener Diode |
| 中文描述： | 250 的低電流運(yùn)算，低反向泄露，低噪聲穩(wěn)壓二極管 |
| 文件頁數(shù)： | 18/76頁 |
| 文件大?。?/td> | 2157K |
| 代理商： | STV2249 |
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STV223XD/224XC - FUNCTIONAL DESCRIPTION
18/76
grounded, the CVBS mode is selected and the
bus control is not active. If the DC level of the
Chroma Input is higher than the SVHS threshold,
then the bus control for the SVHS switch is ac-
tive. Therefore, the SVHS mode can be selected
by hardware using a special SVHS connector
that includes a mechanical switch. In this type of
application, the bus control is set to SVHS mode,
and the CVBS mode is selected by grounding the
Chroma Input pin.
3.2 DEFLECTION PART
– Fully-integrated synchronization separator with a
low pass filter, black level alignment of the CVBS
input, and a 50% slicing level for the synchro-
nized pulse amplitude.
– Vertical output pulse is locked on a pulse that is
twice the horizontal frequency to ensure perfect
interlacing.
– Auto-calibrated VCO using the chroma crystal
reference. Crystal control pin X1/VAMP/
CHROUT indicates the crystal reference value
on Pin XTAL1.
When a 4.43 MHz crystal is connected to
Pin XTAL1, the output load on Pin X1/VAMP/
CHROUT must be greater than 80 k
. When a
3.58 MHz crystal is connected to Pin XTAL1, the
output load must be less than 10 k
.
Two Phase-locked Loops (PLL):
– The first PLL locks the VCO to the video line fre-
quency,
– The second PLL compensates the line transistor
storage time.
Three time constants for the first PLL.
– [X,Y]: Line number referring to the internal line
counter numbering system.
The long time constant is used for normal opera-
tion.
The short time constant is automatically used dur-
ing the VCR search mode and frame retrace when
the frame pulse is outside [258,264] and
[309,314].
The very long time constant is used when there is
no video recognition (very good OSD stability).
Time constants in normal operation (automatic se-
lection of time constants):
– 50 Hz input signal:
short time constant: [306,21],
long time constant: the rest of the field.
– 60 Hz input signal:
short time constant: [0,16],
long time constant: the rest of the field.
Inhibition of the first PLL:
The first PLL is inhibited from line 309 to line 4.5
(or 314) in 50 Hz mode and from line 258 to line
5.5 (or 264) in 60 Hz mode. The time constant val-
ues are chosen by means of external components.
– Possibility of forcing the short time constant dur-
ing the allframe via the bus.
– Possibility of forcing the long time constant dur-
ing the allframe via the bus.
– Possibility of forcing a very long time constant
during the allframe via the bus.
Video identification: independent from PLL1.
The video identification status is available in the
output register of the I2C bus decoder.
Generation of burst gate pulses and line frequency
signals from the first PLL to drive the Chroma and
Video circuits.The burst gate pulse is also sent to
the super-sandcastle generator.
Frame synchronized window:
– large window: [248,352] in AUTO mode,
[248,284] in forced 60 Hz mode, [288,352] in
forced 50 Hz mode.
– narrow window: [309,314] in 50 Hz mode,
[258,264] in 60 Hz mode.
Field frequency selection windows:
– [248,286] 60 Hz mode selection window.
– [288,352] 50 Hz mode selection window.
Frame blanking pulse adapted to standard:
– from line 309 to line 21 in 50 Hz mode,
– from line 258 to line 16 in 60 Hz mode.
Long blanking mode: the end of frame blanking is
line 21 both in 50 and 60 Hz modes. This mode is
useful when the flyback time of the vertical output
stage is longer than the 60 Hz blanking time. It is
used to optimize the 50/60 Hz vertical amplifier ap-
plication due to long frame blanking.
Vertical output pulse duration is 10.5 lines.
Horizontal output pulse: 28 μs line pulse on an
open collector output.
Start-up circuit: the horizontal output is at high lev-
el (disabled) when V
CC1
increases from 0 to 6.0 V
and when V
CCD
has not reached 4 V.
Soft mode circuit: it provides a softer operating
horizontal output with a 75% duty cycle [t
HIGH
/
(t
HIGH
+t
LOW
)]. This results in a smaller conducting
time (16 μs instead of 28 μs).
This mode is active at start-up until two frames af-
ter the V
CC2
reaches 75% of the V
CC1
. It is also
active at shutdown when the V
CC1
floats between
6 V and 5.4 V. And finally, this mode is used if the
V
CC2
drops below 75% of the V
CC1
.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| STV2249C | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:I2C BUS-CONTROLLED MULTISTANDARD SINGLE CHIP TV PROCESSOR |
| STV2249H | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:IC BUS-CONTROLLED MULTISTANDARD SINGLE CHIP TV PROCESSOR |
| STV224X | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:IC BUS-CONTROLLED MULTISTANDARD SINGLE CHIP TV PROCESSOR |
| STV224X_09 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:I?2C bus-controlled multistandard single chip TV processor |
| STV224XC | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:I2C BUS-CONTROLLED MULTISTANDARD SINGLE CHIP TV PROCESSOR |
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