參數(shù)資料
型號: STK14C88-3R45
廠商: Electronic Theatre Controls, Inc.
英文描述: 32K x 8 AutoStore⑩ nvSRAM QuantumTrap CMOS Nonvolatile StaticRAM
中文描述: 32K的× 8自動存儲⑩非易失QuantumTrap的CMOS非易失StaticRAM
文件頁數(shù): 4/13頁
文件大?。?/td> 371K
代理商: STK14C88-3R45
STK14C88-3
November 2003
4
Document Control # ML0015 rev 0.3
SRAM WRITE CYCLES #1 & #2
(V
CC
= 3.0V-3.6V)
e
Note j:
Note k:
Note l:
SRAM WRITE CYCLE #1:
W Controlled
k, l
If W is low when E goes low, the outputs remain in the high-impedance state.
E or W must be
V
during address transitions.
HSB must be high during SRAM WRITE cycles.
SRAM WRITE CYCLE #2:
E Controlled
k, l
NO.
SYMBOLS
PARAMETER
STK14C88-3-35
STK14C88-3-45
STK14C88-3-55
UNITS
#1
#2
Alt.
MIN
MAX
MIN
MAX
MIN
MAX
12
t
AVAV
t
AVAV
t
WC
Write Cycle Time
35
45
55
ns
13
t
WLWH
t
WLEH
t
WP
Write Pulse Width
25
30
40
ns
14
t
ELWH
t
ELEH
t
CW
Chip Enable to End of Write
25
30
40
ns
15
t
DVWH
t
DVEH
t
DW
Data Set-up to End of Write
12
15
25
ns
16
t
WHDX
t
EHDX
t
DH
Data Hold after End of Write
0
0
0
ns
17
t
AVWH
t
AVEH
t
AW
Address Set-up to End of Write
25
30
40
ns
18
t
AVWL
t
AVEL
t
AS
Address Set-up to Start of Write
0
0
0
ns
19
t
WHAX
t
EHAX
t
WR
Address Hold after End of Write
0
0
0
ns
20
t
WLQZi, j
t
WZ
Write Enable to Output Disable
13
15
20
ns
21
t
WHQX
t
OW
Output Active after End of Write
5
5
5
ns
PREVIOUS DATA
DATA OUT
E
ADDRESS
12
t
AVAV
W
16
t
WHDX
DATA IN
19
t
WHAX
13
t
WLWH
18
t
AVWL
17
t
AVWH
DATA VALID
20
t
WLQZ
15
t
DVWH
HIGH IMPEDANCE
21
t
WHQX
14
t
ELWH
12
t
AVAV
16
t
EHDX
13
t
WLEH
19
t
EHAX
18
t
AVEL
17
t
AVEH
DATA VALID
15
t
DVEH
HIGH IMPEDANCE
14
t
ELEH
DATA OUT
E
ADDRESS
W
DATA IN
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STK14C88-3R45I 32K x 8 AutoStore⑩ nvSRAM QuantumTrap CMOS Nonvolatile StaticRAM
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