參數(shù)資料
型號(hào)： STEL-2060CP
英文描述： VITERBI DECODER|QFP|100PIN|PLASTIC
中文描述： 維特比譯碼| QFP封裝| 100引腳|塑料
文件頁(yè)數(shù)： 2/19頁(yè)
文件大小： 284K
代理商： STEL-2060CP
STEL-2060C
2
FUNCTIONAL DESCRIPTION
Convolutional encoding and Viterbi decoding are used to
provide forward error correction (FEC) which improves
digital communication performance over a noisy link. The
STEL-2060C is a specialized product designed to perform
this specific communications related function. At the
encoder a stream of symbols is created which introduces a
high degree of redundancy. This enables accurate decoding
of the information despite a high symbol error rate resulting
from an impaired communications link.
The STEL-2060C contains a K = 7 Viterbi Decoder. The data
inputs can be in offset binary or offset signed-magnitude
formats, with 3-bit soft decision. Auto node sync is provided
for applications where symbol uncertainty can occur. Rate
2
/
3
,
3
/
4
,
4
/
5
,
5
/
6
,
6
/
7
and
7
/
8
punctured signals can be
decoded, as well as non-punctured, Rate
1
/
2
, signals. The
polynomials and puncturing patterns used are industry
standards. Depuncturing logic is incorporated into the
decoder to provide automatic depuncturing of received data
at rates
2
/
3
,
3
/
4
and
7
/
8
when the puncturing patterns
supported by the device are used. A BER monitor is also
provided in the device, along with a circuit for computing
the mean value of the BER over an extended period. These
circuits operate with punctured codes as well as
unpunctured. The STEL-2060C incorporates a descrambler
for signals scrambled with the “Invert G2” algorithm. (With
this method the G2 symbols are logically inverted at the
encoder. This provides a very effective level of scrambling
for the purpose of avoiding long strings of ones or zeroes in
the transmitted signal using BPSK modulation.)
FEATURES
I
45 Mbps Operating Rate
I
Constraint Length K = 7
G
1
= 171
8
G
2
= 133
8
I
Multiple Rates: Rate
1
/
2
as well as
Punctured codes at Rates
2
/
3
through
7
/
8
I
Internal Depuncturing Capability at Rates
2
/
3
,
3
/
4
and
7
/
8
I
Multiple Devices can be Multiplexed to
Give Higher Data Rates
I
Optimized Interface to Operate with BPSK
and QPSK Demodulators
I
Auto Node Sync Capability
I
Differential Decoder
I
“Invert G2” Descrambler
I
Internal BER Monitor and BER
Measurement Circuit
I
5.2 dB Coding Gain @10
-5
BER (R =
1
/
2
)
I
100-pin PQFP Package
I
0.5 Micron CMOS Technology
BLOCK DIAGRAM
SYMBOL
ALIGNMENT
AND
DEPUNCTURING
CIRCUIT
BRANCH
METRIC
ASSIGNMENT
VITERBI
DECODER
(ACS)
TRACEBACK
MEMORY
TIMING AND
CONTROL
G1
G2
PNCG1/G2
DCLKIN
SYNC
RATE
EXTSEL
THRES
DIFFERENTIAL
DECODER
DATO
AUTO
BER
MONITOR
AND
COUNTER
BERR
G1ERR
G2ERR
SYMCKIN
OOS
ODCLK
DDIF
RESET
LDG2
PARL
OBIN
ADDR
WR
INT
3
8
2
3
3
DATA
NODE SYNC
CONTROL
TO ALL REGISTERS
μP
INTERFACE
RD
CSEL
3
DSCRAM
H
8
8
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