
SEC ASIC
iv
STDH90/MDL90
Contents
1
Introduction
1.1 Library Description ................................................................................................................1-1
1.2 Features................................................................................................................................1-2
1.3 CAE Support .........................................................................................................................1-3
1.4 Product Family ......................................................................................................................1-4
1.4.1 Internal Macrocells............................................................................................1-4
1.4.2 Compiled Macrocells ........................................................................................1-4
1.4.3 Input/Output Cells.............................................................................................1-5
1.5 Propagation Delays...............................................................................................................1-6
1.6 Delay Model ..........................................................................................................................1-7
1.7 Testability Design Methodology.............................................................................................1-8
1.8 Maximum Fanouts.................................................................................................................1-9
1.9 Product Line-Up ....................................................................................................................1-10
1.10 Packages Capability by Lead Count ...................................................................................1-11
1.11 External Design Interface Considerations...........................................................................1-12
1.12 Power Dissipation ...............................................................................................................1-13
1.13 VDD/VSS Rules and Guidelines .........................................................................................1-14
1.14 Crystal Oscillator Considerations........................................................................................1-19
2
Electrical Characteristics
DC Electrical Characteristics.........................................................................................................2-1
Input Buffer DC Cruves.................................................................................................................2-3
Output Drive Capabilities ..............................................................................................................2-5
3
Internal Macrocells (Refer to STD90/MDL90)
4
Input/Output Cells
Overview .......................................................................................................................................4-1
Summary Tables ...........................................................................................................................4-2
Input Cells
PHIC/PHICD50/PHICU50 .............................................................................................................4-7
PHIT/PHITD50/PHITU50/PHITU5.................................................................................................4-9
PHITI/PHITID50/PHITIU50 ...........................................................................................................4-11