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參數(shù)資料
| 型號： | STDH90 |
| 英文描述： | Leaded Cartridge Fuse; Current Rating:62.5mA; Voltage Rating:250V; Fuse Terminals:Axial Lead; Fuse Type:Time Delay; Voltage Rating:250V; Body Material:Ceramic; Diameter:6.985mm; Fuse Size/Group:1/4 x 1-1/4 " RoHS Compliant: Yes |
| 中文描述： | STDH90 0.35微米STDH90圖書館|數(shù)據(jù)資料 |
| 文件頁數(shù)： | 12/122頁 |
| 文件大小： | 277K |
| 代理商： | STDH90 |
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Introduction
1.4
Product Family
SEC ASIC
1-6
STDH90/MDL90
1.4
Product Family
STDH90/MDL90 library include the following design elements:
I
I
I
I
Internal Macrocells
Compiled Macrocells
Input/Output Cells
JTAG Boundary Scans.
1.4.1 Internal Macrocells
Macrocells are the lowest level of logic functions such as NAND, NOR and
flip-flop used for logic designs. There are about 430 different types of internal
macrocells. They usually come in three levels of drive strength (1X, 2X and 4X).
These macrocells have many levels of representations—logic symbol, logic
model, timing model, transistor schematic, HSPICE netlist, physical layout, and
placement and routing model.
1.4.2 Compiled Macrocells
Compiled macrocells of STDH90/MDL90 consist of compiled memory and
compiled datapath macrocells.
Compiled memory macrocells include three single-port RAMs (synchronous,
asynchronous and alternative), three dual-port RAMs (synchronous,
asynchronous and alternative) and two ROMs (synchronous diffusion
programmable and via programmable). Synchronous memories have a fully
synchronous operation for clock. Asynchronous memories have a synchronous
operation for Write Enable in write mode and have an asynchronous operation
for address in read mode. Those compiled memories have an automatic
power-down mode that significantly reduces power consumption for read and
write operations. This power-down mode ensures that memory consumes
power for the minimum amount of time needed for a read or write operation.
Some of memories support dual bank option to double the maximum capacity.
Also, Flexible memory apsect ratio is provided. Now, a softmacro based
memory BIST (Built-In Self Test) capability is available. Several memory
macrocells of the same type or the different type in a circuit can be tested by
single BIST circuit.
Compiled datapath macrocells include adder, ALU, barrel shifter, carry select
adder, multiplier and multi-port register file. Adder supports both addition and
subtraction and adopts a group-bypass carry propagation scheme to improve
performance. ALU supports 9 arithmetic operations and 15 logical operations.
Carry select adder is much faster than adder and adopts a double-carry
propagation scheme to improve performance. Multiplier supports pipe-lined
scheme to improve performance and also accumulation scheme. Multi-port
register file allows 1-to-2 write and 1-to-4 read ports and each port is fully
independent. In write mode, this register file operates synchronously for clock.
In read mode, it operates asynchronously for address.
We provide two kinds of engineering design services. One is to support
additional compiled datapath macrocells such as Comparators, Detectors,
Incrementers and Decrementers, Multiplexers, and so on. The other is to
support hardwired datapath module design.
相關(guān)PDF資料 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| STDHCA-1.024 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Crystal Oscillator |
| STDHCA-1.544 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Crystal Oscillator |
| STDHCA-10.000 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Crystal Oscillator |
| STDHCA-11.000 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Crystal Oscillator |
| STDHCA-11.2896 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Crystal Oscillator |
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