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Introduction
1.4 Product Family
Samsung ASIC
1-9
STDH150
1.4.3 COMPILED MEMORY
Today’s System-On-Chip (SoC) designs require various configurations of
embedded memories. These configurations must be optimized for each process
and also optimized for speed, density, and power consumption. Samsung’s
memory compiler, called CubicCompiler, is designed under the efficiency of
custom memory design to achieve optimal designs. Using CubicCompiler is
helpful for designers to perform optimal floorplanning of the design because
designers can evaluate architectural tradeoffs between performance, area and
power by easily varying the aspect ratios, word depths and word widths of their
designs.
Once satisfied with the resulting configuration, CubicCompiler allows designers
to easily generate complete EDA models including functional model, timing
model, physical layout. In STDH150, high-speed compiled memory with best
density is only supported. The high-speed memories are fully optimized for
denser area and are targeted for high-speed applications. Memories in STDH150
are fully user-configurable and are provided as a compiler as follows:
High-Speed Compiled Memories
- Single-port synchronous SRAM
- Single-port synchronous SRAM with bit-write
- Single-port synchronous SRAM with redundancy
- Dual-port synchronous SRAM
- Dual-port synchronous SRAM with bit-write
- Dual-port synchronous SRAM with redundancy
- Multi-port synchronous register file
- Multi-port synchronous register file with bit-write
- Single-port Synchronous Binary CAM
- Single-port Synchronous Ternary CAM
- Single-port synchronous via-1 programmable ROM
- Synchronous First-In First-Out Memory (On-demand)
- High-capacity (Up to 4Mbits) single-port synchronous SRAM with burst
operations (On-demand)
- High-capacity (Up to 4Mbits) single-port synchronous via-1 programmable
ROM (On-demand)
STDH150 compiled memory families adopt most advanced memory design
techniques such as self-controlled timing circuits, partial activation architecture,
multi-stage low power decoding structure and high-sensitivity sense amplifiers
with high stability, to dramatically improve the performance. Such circuits are
extensivelyoptimizedforthespecifiedvoltage,temperatureandprocessandgive
designers high performance and high stability.
All of compiled memories provide edge-triggered synchronous read and write
operations, bit-write or byte write capability, and zero hold time for data-in,
addresses and control pins. Fully static design provides low-voltage data
retention and zero standby current. In case of multi-port register file, 2-port(1-
read/1-writ), 3-port(2-read/1-write) and 4-port(2-read/2-write) are available.