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Samsung ASIC
iv
STD90/MDL90
Contents
1
Introduction
1.1 Library Description................................................................................................................1-1
1.2 Features................................................................................................................................1-2
1.3 CAE Support.........................................................................................................................1-3
1.4 Product Family ......................................................................................................................1-3
1.4.1 Internal Macrocells ....................................................................................................1-3
1.4.2 Compiled Macrocells ................................................................................................1-3
1.4.3 Input/Output Cells......................................................................................................1-4
1.5 Propagation Delays.................................................................................................................1-6
1.6 Delay Model ............................................................................................................................1-12
1.7 Testability Design Methodology...............................................................................................1-15
1.8 Maximum Fanouts...................................................................................................................1-18
1.9 Product Line-Up ......................................................................................................................1-24
1.10 Packages Capability by Lead Count .....................................................................................1-25
1.11 Power Dissipation..................................................................................................................1-27
1.12 V
DD
/V
SS
Rules and Guidelines..............................................................................................1-30
1.13 Crystal Oscillator Considerations..........................................................................................1-35
2
Electrical Characteristics
DC Electrical Characteristics.........................................................................................................2-1
Input Buffer DC Curves.................................................................................................................2-5
Output Drive Capabilities...............................................................................................................2-7
3
Internal Macrocells
Overview .......................................................................................................................................3-1
Summary Tables ...........................................................................................................................3-2
Logic Cells
AD2DH/AD2/AD2D2/AD2D4.........................................................................................................3-15
AD3DH/AD3/AD3D2/AD3D4.........................................................................................................3-17
AD4DH/AD4/AD4D2/AD4D4.........................................................................................................3-19
AD5/AD5D2/AD5D4......................................................................................................................3-22
ND2DH/ND2/ND2D2/ND2D4........................................................................................................3-25
ND3DH/ND3/ND3D2/ND3D4........................................................................................................3-27
ND4DH/ND4/ND4D2/ND4D2B/ND4D4.........................................................................................3-30