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1.4 Product Family
Introduction
STD90/MDL90
1-4
Samsung ASIC
scheme to improve performance and also accumulation scheme. Multi-port
register file allows 1-to-2 write and 1-to-4 read ports and each port is fully
independent. In write mode, this register file operates synchronously for clock. In
read mode, it operates asynchronously for address.
We provide two kinds of engineering design services. One is to support
additional compiled datapath macrocells such as Comparators, Detectors,
Incrementers and Decrementers, Multiplexers, and so on. The other is to support
hardwired datapath module design.
1.4.3 INPUT/OUTPUT CELLS
There are about four hundred different I/O buffers. Each I/O cell is implemented
solely on the basic I/O cell architecture which forms the periphery of a chip.
A test logic is provided to enable the efficient parametric (threshold voltage)
testing on input buffers including LVCMOS, CMOS and TTL level converters,
Schmitt trigger input buffers, clock drivers and oscillator buffers. Pull-up and pull-
down resistors are optional features.
Three basic types of output buffers (non-inverting, tri-state and open drain) are
available in a range of driving capabilities from 1mA to 24mA for 3.3V drive and
1mA to 6mA for 5V-tolerant drive. One or two levels of slew rate controls are
provided for each buffer type (except 1mA and 2mA buffers) to reduce output
power/ground noise and signal ringing, especially in simultaneous switching
outputs.
Bi-directional buffers are combinations of input buffers and output buffers (tri-
state or open drain) in a single unit. The I/O structure has been fully
characterized for ESD protection and latch-up resistance.
For user’s convenience, STD90/MDL90 library provides 100K
pull-down and
pull-up resistances respectively.
1.4.3.1 I/O Cell Drives Options
To provide designers with the greater flexibility, each I/O buffer can be selected
among various current levels (e.g., 1mA, 2mA,..., 24mA). The choice of current-
level for I/O buffers affects their propagation delay and current noise.
The slew rate control helps decrease the system noise and output signal
overshoot/undershoot caused by the switching of output buffers. The output
edge rate can be slowed down by selecting the high slew rate control cells.
STD90/MDL90 provides three different sets of output slew rate controls. Only
one I/O slot is required for any slew rate control options.
1.4.3.2 5V Tolerant I/O Buffers
STD90/MDL90 library is a process which has the most optimum performance in
3.3V. In this process, voltages more than 3.6V are not allowed at the gate oxide
because of a reliability problem. And a special circuit is adopted in order to make
pin voltage tolerable up to 5.25V and to offer TTL interface driving up to 6mA.
Obviously, this circuit is constructed not to permit more than 3.6V at the gate
oxide. The external circuit diagram is as follows.
The maximum external tolerance voltage of this buffer is 5.5V. And the leakage
current of tri-state input pin and output pin is less than 100nA in 0 ~ 5V. It can be
used as a 3.3V normal buffer.