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SEC ASIC
4-159
STD80/STDM80
CARDBUS I/O BUFFERS
Overview
CardBus I/O buffers have 3.3V operation, 32-bit bus width and 33MHz of transmission speed. The latest
version of the PC card standard adds information to improve compatibility with the standard by requiring a
Card Information Structure (CIS) on every PC card.
The standard has also been enhanced to support the following optional features:
– Low-Voltage Only Operation (3.3V)
– Hardware Direct Memory Access (DMA)
– Multiple-Function Cards
– Industry Standard Power Management Interface (APM)
– High Throughput 32-Bit Bus Mastering Interface (CardBus)
SEC ASIC supports nine different CardBus I/O buffers. If necessary, a Voltage Detector cell can be used
with them. For maximum flexibility, CardBus I/O buffers have not only a Level Shifter but also a pull-up
enable control pin.
CardBus I/O buffers have only 3.3V electrical specifications, however, we can support 5V/3.3V flexible
operation by using of a level shifter. Regardless of the I/O voltage, S3V5V pin controls the same input level
and output driving current. S3V5V pin should be tied to the voltage detector in a mixed system, or ground in
a 3.3V-only system.
We can not attribute a level shifter to PUEN (Pull-Up Enable) pin, because we have only four level shifters.
In order to control the PUEN pin with an internal signal, you should use the level shifter butter (PLSCB) in a
mixed system.
For minimizing power consumption, CardBus I/O buffers have a nand type input with a control pin.
Therefore, the input buffers operate as active-high input buffers. However, if the control pin is in low state,
the output Y is low and not tri-state.
General Description
The CardBus I/O buffer is controlled by S3V5V signal that is logically low in a 5V operation and logically high
in a 3.3V operation. If you use a voltage detector cell with the CardBus I/O buffer, you have to connect this
S3V5V pin to VDET (voltage detector) output. Do not use a level shifter buffer (PLSCB).
CSTSCHG Buffer Specification
The CSTSCHG pin can be used by the CardBus PC card to remotely power up the system. The design of
the CardBus PC card’s output buffer and the system’s input buffer must ensure no electrical damage results.
– An output buffer for CSTSCHG pin never exceed 1mA.
– An input buffer for CSTSCHG pin is able to withstand sustained forward bias current of 1mA.
CCLK Specification
The electrical characteristics of CCLK follows 3.3V signalling of PCI Local bus specification Revision 2.1.
Refer to the PCI buffer electrical characteristics.