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INTRODUCTION TO STD80/STDM80
CRYSTAL OSCILLATOR CONSIDERATIONS
SEC ASIC
1-31
STD80/STDM80
C1 / C2 SELECTION
Optimal values for the capacitors C1 and C2 depend
on whether a quartz crystal or ceramic resonator is
being used, and also on application-specific
requirements on start-up time and frequency
tolerance.
Start-up time is sometimes more critical in
microcontroller systems than frequency stability,
because of various reset and initialization
requirements.
Less commonly, accuracy of the oscillator frequency is
also critical, for example, when the oscillator is being
used as a time base. As a general rule, fast start-up
and stable frequency tend to pull the oscillator design
in opposite directions.
Considerations of both start-up time and frequency
stability over temperature suggest that C1 and C2
should be about equal and at least 20pF. (But they
don’t have to be either.)
Increasing the value of these capacitances above
some 40 or 50pF improves frequency stability. It also
tends to increase the start-up time. These is a
maximum value (several hundred pH, depending on
the value of R1 of the quartz or ceramic resonator)
above which the oscillator won’t start up at all.
If the on-chip amplifier is a simple inverter, the user
can select values for C1 and C2 between some 20 and
100pF, depending on whether start-up time or
frequency stability is the more critical parameter in a
specific application.
RF / RX SELECTION
A CMOS inverter might work better in this application
since a large Rf (1mega-ohm) can be used to hold the
inverter in its linear region.
Logic gates tend to have a fairly low output resistance,
which testabilizes the oscillator. For that reason a
resistor Rx (several k-ohm) is often added to the
feedback network, as shown in Figure 1-31. CMOS
Oscillator.
At higher frequencies a 20 or 30pF capacitor is
sometimes used in the Rx position, to compensate for
some of the internal propagation delay.
PIN CAPACITANCE
Internal pin-to-ground and pin-to-pin capacitances,
and PADA and PADY have some effect on the
oscillator. These capacitances are normally taken to
be in the range of 5 to 10pF, but they are extremely
difficult to evaluate. Any measurement of one such
capacitance necessarily include effects from the
others.
One advantage of the positive reactance oscillator is
that the pin-to ground cap. is paralleled by an external
bulk capacitance, so a precise determination of their
value is unnecessary.
We would suggest that there is little justification for
more precision than to assign them a value of 7pF
(PADA-to-ground and PADA-to-PADY). This value is
probably not in error by more than 3 or 4pF.
The PADY-to-ground cap. is not entirely a “pin
capacitance”, but more like an “equivalent output
capacitance” of some 25 to 30pF, having to include the
effect of internal phase delays. This value varies to
some extent with temperature, process, and
frequency.
PLACEMENT OF COMPONENTS
Noise glitches arising at PADA or PADY pins at the
wrong time can cause a miscount in the internal
clock-generating circuitry. These kinds of glitches can
be produced through capacitive coupling between the
oscillator components and PCB traces carrying digital
signals with fast rise and fall times.
For this reason, the oscillator components should be
mounted close to the chip and have short, direct
traces to the PADA, PADY, and V
SS
pins.
If possible, use dedicated V
SS
and V
DD
pin for only
crystal feedback amplifier.