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SEC ASIC
xi
STD80/STDM80
Latch .............................................................................................................................................6-74
Multiplexer.....................................................................................................................................6-82
NAND/AND....................................................................................................................................6-85
NOR/OR........................................................................................................................................6-87
OR-AND........................................................................................................................................6-89
OR-AND-INVERT..........................................................................................................................6-91
Tri-State Buffer/Inverter.................................................................................................................6-93
XNOR/XOR...................................................................................................................................6-95
7
JTAG Boundary Scans
Overview .......................................................................................................................................7-1
Boundary Scan Architecture..........................................................................................................7-2
Boundary Scan Register Macrocells.............................................................................................7-4
JTBI1 ....................................................................................................................................7-5
JTCK.....................................................................................................................................7-12
JTIN1....................................................................................................................................7-14
JTINT1..................................................................................................................................7-18
JTOUT1................................................................................................................................7-24
JTAG Tap Controller Macrofunction..............................................................................................7-28
Instruction Register/Decoder Macrofunction.................................................................................7-31
Implementation of IEEE P1149.1/JTAG........................................................................................7-32
System Clock Considerations .......................................................................................................7-32