- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄372309 > ST6388 (意法半導(dǎo)體) 8-BIT MCUs WITH ON-SCREEN-DISPLAY FOR TV TUNING PDF資料下載
參數(shù)資料
| 型號(hào)： | ST6388 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 8-BIT MCUs WITH ON-SCREEN-DISPLAY FOR TV TUNING |
| 中文描述： | 8位微控制器對(duì)屏幕，電視調(diào)諧顯示器 |
| 文件頁(yè)數(shù)： | 57/82頁(yè) |
| 文件大?。?/td> | 718K |
| 代理商： | ST6388 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)當(dāng)前第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)
57/82
ST6380, ST6381, ST6382, ST6383, ST6388, ST6389
ON-SCREEN DISPLAY
(Cont’d)
4.8.3 Application Notes
1- The OSD character generator is composed of a
dual port video ram and some circuitry. It needs
two input signals VSYNC and HSYNC to synchro-
nize its dedicated oscillator to the TV picture. It
generates 4 output signals, that can be used from
the TV set to generate the characters on the
screen. For instance, they can be used to feed the
SCART plug, providing an adequate buffer to drive
the low impedance (75 ohm) of the SCART inputs.
2 - The Core sees the OSD as a number of RAM
locations (168) plus a certain number of control
registers (8). 175 of these locations are mapped in
one page of the dynamic data ram address range
(0h...3Fh).
The page 5 (20h value loaded into the register
0E8h) is further subdivided in 4 pages (using bits
LS1 and LS0) in order to allow access to all 168
bytes of the OSD RAM within the allowed address
range. According to the value of these two bits we
shall a first line (selected among lines 0, 2, 4 or 6)
mapped onto the 0h-14h address range, and a
second line (selected among lines 1, 3, 5 or 7)
mapped onto the 20h-34h address range.
The global registers in page 5 are accessible at
RAM locations 38h-3Fh, page 5 selected via DR-
BR, regardless of the value of the LS0/LS1 bits.
3 - The video RAM is a dual port ram. That means
that it can be addressed either from the Core or
from the OSD circuitry itself. To reduce the com-
plexity of the circuitry, and thus its cost, some re-
strictions have been introduced in the use of the
OSD.
a.
The Core can access 6 of the global registers
(addresses 38h - 3Dh in page 5) only when the
OSD oscillator is OFF (GE bit not set). Only
the last location (control register 3Fh in page
5) can be addressed at any time. This is the
Global Enable Register, which contains the
GE and ORE bits. If the GE bit is set, the OSD
is on, if it is reset the OSD is off.
c.
The Core can write to the 168 locations of
OSD RAM only when the ORE bit is not set.
This bit must be set before the first active line
of OSD display (which displays characters).
This line follows the VSYNC active period and
is delayed by a time equal to the Vertical Start
register value multiplied by the duration of one
display line (64
μ
s for the usual TV standard).
4 - The timing of the on/off switching of the OSD
oscillator is the following:
a.
GE bit is set. The OSD oscillator will start on
the next VSYNC signal.
b.
GE bit is reset. The OSD oscillator will be im-
mediately switched off.
To avoid a bad visual impression, it is important
that the GE bit is set before the end of the flyback
time when changing characters. This can be done
inside the VSYNC interrupt routine. The following
diagram can explain better: OSD Oscillator ON/
OFF Timing
Figure 32. OSD Oscillator ON/OFF Timing
Notes:A - Picture time: 20 mS in PAL/SECAM.
B - VSYNC interrupt, if enabled.
C - Starting of OSD oscillator, if GE = 1.
D - Flyback time.
When modifying the picture display (i.e.: a bar
graph for an analog control), it is important that the
switching on of the GE bit is done before the end
of the flyback time (D in
Figure 32
). If the GE bit is
set after the end of the flyback time then the OSD
will not start until the beginning of the next frame.
This results in one frame being lost and will result
in a flicker on the screen. One method to be sure
to avoid the flicker is to wait for the VSYNC inter-
rupt at the start of the flyback; once the VSYNC in-
terrupt is detected, then the GE and ORE bits can
be set to zero, the global control registers
changed, if necessary, and the GE set to one. All
this should occur before the end of the flyback time
in order not to lose a frame. The correct edge of
the interrupt must be chosen. The characters in
RAM can be changed until the last line before the
active screen area and then the ORE bit must be
set.
time
VSYNC
B
V
C
V
E
V
A
D
VA00344
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ST6389 | 8-BIT MCUs WITH ON-SCREEN-DISPLAY FOR TV TUNING |
| ST63RS1 | 8-BIT MICROCONTROLLER |
| ST63RT1 | 8-BIT MICROCONTROLLER |
| ST6400C1003 | CONTROLLER CHRONOTHERM |
| ST650C20L1 | THYRISTOR 1557A |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ST6388B1 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8-BIT MCUs WITH ON-SCREEN-DISPLAY FOR TV TUNING |
| ST6388B4 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8-BIT MCUs WITH ON-SCREEN-DISPLAY FOR TV TUNING |
| ST6389 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8-BIT MCUs WITH ON-SCREEN-DISPLAY FOR TV TUNING |
| ST6389B1 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8-BIT MCUs WITH ON-SCREEN-DISPLAY FOR TV TUNING |
| ST6389B4 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8-BIT MCUs WITH ON-SCREEN-DISPLAY FOR TV TUNING |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。