參數(shù)資料
型號: ST6388
廠商: 意法半導(dǎo)體
英文描述: 8-BIT MCUs WITH ON-SCREEN-DISPLAY FOR TV TUNING
中文描述: 8位微控制器對屏幕,電視調(diào)諧顯示器
文件頁數(shù): 52/82頁
文件大?。?/td> 718K
代理商: ST6388
52/82
ST6380, ST6381, ST6382, ST6383, ST6388, ST6389
ON-SCREEN DISPLAY
(Cont’d)
Table 18. OSD Control Registers and Data RAM
Addressing
OSD Global Enable Register
This register contains the global enable bit (GE),
OSD Ram Enable bit (ORE) and the line select bits
(LS1/LS0). This register can be written at any time.
It is a write only register.
OSD Global Enable Bit Register (OGER)
Address: 3Fh - Page 5
Write Only
D7-D4
. These bits are not used
GE.
Global Enable. This bit allows the entire dis-
play to be turned off.
“0” The entire display is disabled. The other regis-
ters of the OSD can be accessed by the Core.
“1” Display of words is controlled by the word en-
able bits (WE) located in the format or space
character. The other registers cannot be ac-
cessed by the Core.
ORE.
OSD Ram Enable. This bit controls the ac-
cess to the OSD RAM.
“0” The OSD RAM can be accessed by the Core.
“1” The OSD RAM content is displayed on screen
and cannot be accessed by Core.
Note
: The display of characters on screen is only
possible after the setting of these two bits
LS1-LS0.
This bits selects one pair of OSD RAM
lines that is to be mapped into the 0h-35h address
area. There are four possible values of this pair of
bits:
“00” - selects line 0 and line 1;
“01” - selects line 2 and line 3;
“10” - selects line 4 and line 5;
“11” - selects line 6 and line 7.
Note
: The global registers in page 5 are accessi-
ble at RAM locations 38h-3Fh, page 5 selected,
regardless of the value of the LS0/LS1 bits.
OSD Polarity Select Register (OPSR)
Address: EDh - Static Page
— Write Only
D7-D4
. These bits are reserved and must always
be written with 0.
VSP
. Vertical sync polarity input select bit. This bit
selects the polarity of the VSync input signal (“0”
for positive, “1” for negative polarity, respectively).
HSP
. Horizontal sync input polarity select bit. This
bit selects the polarity of the HSync input signal
(“0” for positive, “1” for negative polarity, respec-
tively).
BLKP
. Blanking output polarity select bit. This bit
selects the polarity of the BLK output (“0” for posi-
tive, “1” for negative polarity, respectively).
RGBP
. RGB output polarity select bit. This bit se-
lects the polarity of the RGB outputs (“0” for posi-
tive, “1” for negative polarity, respectively).
Note:
Reset value is 00h, all polarities being posi-
tive.
Page
Page 5
Page 5
Page 5
Page 5
Page 5
Page 5
Page 5
Page 5
Page 5
Static
page
Address
00h - 14h
20h - 34h
38h
39h
3Ah
3Bh
3Ch
3Dh
3Fh
Register or RAM
RAM Locations 00h - 14h
RAM Locations 20h - 34h
Vertical Start Register
Horizontal Start Register
Vertical Space Register 0
Horizontal Space Register
Background Control Register
Vertical Space Register 1
Global Enable Register
EDh
OSD Polarity Select Register
7
0
D7
D6
D5
D4
LS1
LS0
ORE
GE
7
0
D7
D6
D5
D4
VSP
HSP
BLKP
RGBP
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