參數(shù)資料
型號： ST52F514F0M6
英文描述： IC MAX 7000 CPLD 160 100-TQFP
中文描述： 微控制器
文件頁數(shù)： 102/106頁
文件大?。?/td> 648K
代理商： ST52F514F0M6
ST52F510/F513/F514
102/106
15.5 SPI Register Description
In the following sections describe the registers
used by the SPI. In the 16 pin devices the SPI is
not present and the described register aren’t used
15.5.1 SPI Configuration Registers.
SPI ControlRegister (SPI_CR)
Configuration Register 20 (014h) Read/Write
Reset Value: 0000 0000 (00h)
Bit 7:
SPIE
Serial peripheral interrupt enable.
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SPI interrupt is generated whenever
SPIF=1 orMODF=1 in SPI_STATUS_CR
Bit 6:
SPE
Serial peripheral output enable.
This bit is set and cleared by software. It is
also cleared by hardware when, in master
mode, SS=0 (see Section 15.4.5 Master
Mode Fault).
0: I/O port connected to pins
1: SPI alternate functions connected to pins
Note:
The SPE bit is cleared by reset, so the SPI
peripheral is not initially connected to the pins.
Bit 5:
SPR2
Divider Enable.
This bit is set and cleared by software and it
is cleared by reset. It is used with the
SPR[1:0] bits to set the baud rate. Refer to
Table 15.1.
0: Divider by 2 enabled
1: Divider by 2 disabled
Note:
This bit has no effect in slave mode.
Bit 4:
MSTR
Master/Slave mode select.
This bit is set and cleared by software. It is
also cleared by hardware when, in master
mode, SS=0 (see Section 15.4.5 Master
Mode Fault).
0: Slave mode is selected
1: Master mode is selected, the function of
the SCK pin changes from an input to an
output and the functions of the MISO and
MOSI pins are reversed.
Bit 3:
CPOL
Clock polarity.
This bit is set and cleared by software. This
bit determines the steady state of the serial
Clock. The CPOL bit affects both the master
and slave modes.
0: The steady state is a low value at the SCK
pin.
1: The steady state is a high value at the SCK
pin.
Note:
SPI must be disabled by resetting the SPE
bit if CPOL is changed at the communication byte
boundaries.
Bit 2:
CPHA
Clock phase.
This bit is set and cleared by software.
0: The first clock transition is the first data
capture edge.
1: The second clock transition is the first
capture edge.
Bit 1-0:
SPR1
-
SPR0
Serial peripheral rate.
These bits are set and cleared by software.
Used with the SPR2 bit, they selectone of six
baud rates to be used as the serial clock
when thedevice isa master(see Table 15.1).
These 2 bits have no effect in slave mode.
Remark:
It is recommended to write the SPI_CR
register after the SPI_STATUS_CR register.
SPI Control-Status Register (SPI_STATUS_CR)
Configuration Register 21 (015h) Read/Write
Reset Value: 0000 0000 (00h)
7
0
SPIE
SPE
SPR2
MSTR
CPOL
CPHA
SPR1
SPR2
Table 15.1 Serial Peripheral Baud Rate
Serial Clock
f
CPU
/2
f
CPU
/4
f
CPU
/8
f
CPU
/16
f
CPU
/32
f
CPU
/64
SPR2
1
0
0
1
0
0
SPR1
0
0
0
1
1
1
SPR0
0
0
1
0
0
1
7
0
SPIF
WCOL
OR
MODF
-
SOD
SSM
SSI
相關(guān)PDF資料
PDF描述
ST52F514F1B6 IC MAX 7000 CPLD 160 100-TQFP
ST52F514F1M6 IC MAX 7000 CPLD 256 208-PQFP
ST52F514F3B6 IC MAX 7000 CPLD 256 208-PQFP
ST52F514F3M6 IC MAX 7000 CPLD 256 256-FBGA
ST52F514G0B6 IC MAX 7000 CPLD 256 256-FBGA
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ST52F514F1B6 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller
ST52F514F1M6 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller
ST52F514F3B6 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller
ST52F514F3M6 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller
ST52F514FMB6 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8-BIT INTELLIGENT CONTROLLER UNIT ICU Two Timer/PWMs, ADC, I2C, SPI, SCI
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*