參數(shù)資料
型號： ST2202
廠商： Electronic Theatre Controls, Inc.
英文描述： 8 BIT Integrated Microcontroller with 256K Bytes ROM
中文描述： 8位微控制器集成256K字節(jié)ROM的
文件頁數(shù)： 48/65頁
文件大?。?/td> 1946K
代理商： ST2202
Sitronix
17.3 SPI Control/Status Registers
ST2202
Ver 2.0a
48/65
2003-May-05
SPI control and status registers are summarized in TABLE 17-1.
TABLE 17-2 Summary Of SPI Control Registers
R/W Bit 7/15 Bit 6/14 Bit 5/13 Bit 4/12 Bit 3/11 Bit 2/10 Bit 1/9
R/W
SD[7]
SD[6]
SD[5]
SDATAH
R/W
SD[15]
SD[14]
SD[13]
SCTR
R/W
SPIEN
RXIEN
ERIEN MEREN DRINV
SCKR
R/W
-
SCK[2]
SCK[1]
R
-
RXRDY TXEMP
SSR
W
PCC
R/W
PCC[7]
PCC[6]
PCC[5]
PFC
R/W
RXD0
TXD0
SRDY
IREQH
R/W
-
-
-
IENAH
R/W
-
-
-
Address
$050
$051
$052
$053
Name
SDATAL
Bit 0/8
SD[0]
SD[8]
SMOD
BC[0]
BCERR
Default
0000 0000
-000 0000
-000 -000
0000 0000
0000 0000
- - - - 0000
- - - - 0000
SD[4]
SD[12]
SD[3]
SD[11]
SD[2]
SD[10]
POL
BC[2]
MDERR OERR
SD[1]
SD[9]
PHA
BC[1]
SCK[0]
SBZ
BC[3]
-
$054
Write any value to reset SSR
PCC[4]
SS
-
-
$00A
$00D
$03D
$03F
PCC[3]
MOSI
IRURX
IEURX
PCC[2]
MISO
IRUTX
IEUTX
PCC[1]
SCK
IRSRX
IESRX
PCC[0]
INTX
IRSTX
IESTX
17.3.1 SPI Data Registers
TABLE 17-3 SPI Data Registers
Bit 6/14
Bit 5/13
SD[6]
SD[5]
SD[14]
SD[13]
Address Name
$050
$051
Bit 7~0:
Write
: Write low byte data to transmit buffer / clear status bit
TXEMP
/ trigger an data exchange
Read
: Read low byte data from receive buffer / clear status bit
RXRDY
Bit 15~8:
Write
: Write high byte data to transmit buffer /
Read
: Read high byte data from receive buffer
R/W Bit 7/15
Bit 4/12
SD[4]
SD[12]
Bit 3/11
SD[3]
SD[11]
Bit 2/10
SD[2]
SD[10]
Bit 1/9
SD[1]
SD[9]
Bit 0/8
SD[0]
SD[8]
Default
0000 0000
0000 0000
SDATAL
R/W
SDATAH
R/W
SD[7]
SD[15]
17.3.2 SPI Control Register
TABLE 17-4 SPI Control Register
Bit 6
Bit 5
RXIEN
ERIEN
Address Name R/W
$052
SCTR
Bit 7:
SPIEN
:
SPI control bit
0
= SPI disable
1 = SPI enable
Bit 6:
RXIEN
:
Receive buffer ready interrupt control bit
0
= Receive buffer ready interrupt disable
1 = Receive buffer ready interrupt enable
Bit 5:
ERIEN
:
Two error interrupts control bit
0
= Two error interrupts disable
1 = Two error interrupts enable
Bit 4:
MEREN
:
Mode fault detection control bit
0
= Mode fault detection disable
1 = Mode fault detection enable
Bit 3:
DRINV :
DATA_READY
active level selection bit
0
= Active level is high
1 = Active level is low
Bit 2~1:
SPHA/SPOL :
SPI clock polarity and phase control bits
Refer to section 17.1.1
Bit 0:
SMOD :
Master / Slave modes selection bit
0
= Select slave mode
1 = Select master mode
Bit 7
SPIEN
Bit 4
MEREN
Bit 3
DRINV
Bit 2
POL
Bit 1
PHA
Bit 0
SMOD
Default
0000 0000
R/W
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