參數(shù)資料
型號(hào)： ST2202
廠商： Electronic Theatre Controls, Inc.
英文描述： 8 BIT Integrated Microcontroller with 256K Bytes ROM
中文描述： 8位微控制器集成256K字節(jié)ROM的
文件頁數(shù)： 46/65頁
文件大小： 1946K
代理商： ST2202
Sitronix
ST2202
Ver 2.0a
46/65
2003-May-05
MSB
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
LSB
MSB
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
LSB
POL = 0
POL = 1
Output From Master
(MOSI)
From Master
Output From Slave
(MISO)
SS
FIGURE 17-2 Transmission Format (PHA = 0)
MSB
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
LSB
MSB
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
LSB
POL = 0
POL = 1
Output From Master
(MOSI)
From Master
Output From Slave
(MISO)
SS
FIGURE 17-3 Transmission Format (PHA = 1)
17.1.2 Transmit Buffer and Receive Buffer
Operations of transmit and receive buffers are discussed
below.
Transmit Buffer
The transmit buffer is 16-bit long, and is write-only. This
buffer is empty after the SPI was enabled at the beginning.
In the meantime, the transmit buffer empty flag
TXEMP
(
SSR[5]
) will be set to indicate the status of buffer. Up to 16
bits of data can be filled with writes to SPI data registers
(
SDATAL
and
SDATAH
).
TXEMP
will be cleared after
SDATAL
is wrote a value (Writing
SDATAH
will not affect
TXEMP
). Once the shift register proceeds to exchange,
data in buffer will be loaded into shift register and
TXEMP
will be set again. Meanwhile a SPI transmitter interrupt will
be issued and the transmit buffer can be filled with new
data for next transmission.
The receive buffer is 16-bit long, and is read-only. This
buffer is empty after the SPI was enabled first. In the
meantime, the receive buffer ready flag
RXRDY
(
SSR[6]
)
will be cleared to indicate status of buffer. Two bytes of data
can be read from
SDATAL
and
SDATAH
. After completing
exchange, data in shift register will be loaded into receive
buffer, and then
RXRDY
will be set to indicate that the
received data is available. Next,
RXRDY
should be cleared
by one read instruction to
SDATAL
(Reading
SDATAH
will
not affect
RXRDY)
. In case of master mode, if one
completed data is moving into receive buffer and
RXRDY
is
still set, the moving activity will no stop but the receive
buffer overrun flag
OERR
(
SSR[1]
) will be set to indicate
that an old data is overwrote. If it is in slave mode, the
receive buffer will not be overwrote while
OERR
equals “1”.
OERR
can be cleared by reading
SDATAL
or by any write
to
SSR
.
Receive Buffer
17.1.3 Master, Slave Modes and The Shift Register
The SPI can operate in master or slave mode according to
SMOD
(
SCTR[0]
). These two modes and operations of the
shift register for each are discussed below.
Master Mode
The SPI operates as a master device when setting
SMOD
.
In this mode, communication clock is provided by ST2202
with SCK (PC1). If there may have more than one master
connected, bus contention can be detected by setting mode
fault detection bit
MEREN
(
SCTR[4]
).
SS
signal should be
input and pulled high temporarily during this detection.
Once
SS
inputs low level, a mode fault status can be
reported at
MDERR
(
SSR[2]
).
Some SPI devices have
DATA_READY
output to suspend
the incoming transmission. Setting
SRDY
(
PFC[5]
) may
include timing of
DATA_READY
, while clearing this bit to
discard it. Communication clock and data transmission only
starts after
DATA_READY
returns to low level. The active
level of
DATA_READY
can be inverted to be high level
active by setting inversion control bit
DRINV
(
SCTR[3]
).
When transmission, data in shift register will be shifted to
master data output MOSI (PC3) with most significant bit
(MSB) first, while data from serial data input MISO (PC2)
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