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| 型號： | ST2202 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 8 BIT Integrated Microcontroller with 256K Bytes ROM |
| 中文描述： | 8位微控制器集成256K字節(jié)ROM的 |
| 文件頁數(shù)： | 45/65頁 |
| 文件大?。?/td> | 1946K |
| 代理商： | ST2202 |
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Sitronix
ST2202
Ver 2.0a
45/65
2003-May-05
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The ST2202 contains one serial peripheral interface (SPI)
module to interface with external devices, such as Flash
memory, analog-to-digital converter, and other peripherals,
including another ST2202. The SPI consists of a master- or
slave-configurable interface so that connections of both
master and slave devices are allowable. Five signals
multiplexed with Port-C are used by SPI. With equipped
DATA_READY
and
SS
(slave-select) control signals and
transmit/receive buffers, faster data exchange with fewer
software interrupts is easy to be made. Data length is
widely supported from 7-bit up to 16-bit to satisfy various
applications. One clock generator is provided for the
synchronous communication clock SCK, which is sourced
from OSCK. FIGURE 17-1 illustrates the block diagram of
SPI.
CPU Interface
Clock
Generator
16-bit Shift Register
(MSB First)
16-bit Transmit
Buffer
16-bit Receive
Buffer
MOSI
MISO
Interface
Control
SCK
OSCK
DATA_READY
SPICK
SS
FIGURE 17-1 SPI Block Diagram
17.1 SPI Operations
The SPI contains one 16-bit shift register and two 16-bit
buffers for transmission and receiving respectively. Data
with variable length from 7-bit to 16-bit can be exchanged
with external devices through two data lines. Data length is
controlled by bit count register
BC[3:0]
(bit3~0 of SPI clock
control register
SCKR)
. The current exchange will be over
while the exchanged bit number reaches bit count setting.
The synchronous communication clock SCK is used to
synchronize two devices and transfer data in and out of the
shift register. Data is clocked by SCK with a programmable
data rate, which is assigned by
SCK[2:0]
(bit6~4 of SPI
clock control register
SCKR
). Refer to TABLE 11-7 for all
clock rate settings.
17.1.1 Clock Phase and Polarity Controls
Four combinations of serial clock (SCK) phase and polarity
are selectable by two control bits
PHA
and
POL
(bit 2~1 of
SPI control register
SCTR
). FIGURE 17-2 and FIGURE
17-3 show the transmission format of two phase settings.
The SPI block is controlled by
SPIEN
(
SCTR[7]
). Setting
SPIEN
will enable SPI function and the clock divider. Then
the internal states of SPI will be reset to initial values. After
that, write data to
SDATAL
will initiate an exchange. While
exchanging, the busy flag will be set and is reported in
SBZ
(bit 4 of SPI status register
SSR
).
A slave select signal
SS
(multiplexed with PC4) is used to
identify individual selection of a slave SPI device. Slave
devices that are not selected do not interfere with SPI bus
activities. For a master SPI device,
SS
can be used to
indicate a multiple-master bus contention which can be
reported in mode fault bit
MDERR
(bit3 of SPI status
register
SSR
).
Note:
The clock settings should be identical for
master and the communicating slave device.
In this mode, both master and the communicating slave
should present MSB after the falling edge of
SS
. Then the
first edge of SCK will be the first capture strobe of input
data. If
POL
=0, this first edge is rising edge; if
POL
=1, it will
be a falling edge.
Transmission Format – PHA = 0
In this mode, both master and the communicating slave will
be ready after the falling edge of
SS
. The two output MSB
at the first edge of SCK. Then the second edge will be the
capture strobe. If
POL
=0, the first edge is rising edge; if
POL
=1, it will be a falling one.
Transmission Format – PHA = 1
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