參數(shù)資料
型號: ST2202
廠商: Electronic Theatre Controls, Inc.
英文描述: 8 BIT Integrated Microcontroller with 256K Bytes ROM
中文描述: 8位微控制器集成256K字節(jié)ROM的
文件頁數(shù): 41/65頁
文件大?。?/td> 1946K
代理商: ST2202
Sitronix
external DC-DC converter, which generates a high voltage
for driving liquid crystal.
POFF
outputs “1” when clearing
LPWR
(
LCTR
), and outputs “0” by setting this bit, which is
also the default value.
BLANK (Contrast control)
The LCD blank signal is used to control the contrast of
display by setting contrast level in
LPWM[5:0]
with “00000”
(default) represents a maximum level and “11111” is for
minimum. The
BLANK
signal achieves this function by
outputting a PWM signal according to the settings of
16.2 Mapping the Display Data
ST2202
Ver 2.0a
41/65
2003-May-05
contrast. Refer to section 16.4.10 for more information.
Besides contrast control,
BLANK
signal plays another role
of turning display off. This is controlled by register bit
BLNK
(
LCTR
). Setting
BLNK
bit will make
BLANK
signal to
output “0” to blank the display regardless of contrast control.
Setting
BLNK
bit will enable the PWM contrast control and
of course the
BLANK
signal. If
LPWMTR[5:0]
are all zeros,
BLANK
signal will stay at high level with no PWM
modulation.
The screen width and height of the LCD panel are
programmable through software. FIGURE 16-1 illustrates
the relationship between the portion of a large graphics file
displayed on the screen and the actual page. Although the
maximum screen size can be up to 1024x512, the actual
supported resolution is limited by the display buffer size,
which is also the internal RAM size, 4K bytes. Each bit in
the display memory corresponds to a pixel in the LCD panel.
FIGURE 16-1 also shows the mapping of the display data
to the LCD.
FIGURE 16-1 LCD Screen Format
16.3 LCD Interface Timing
The LCD controller continuously pumps the pixel data into
the LCD panel via the LCD data bus. The bus is timed by
the CP, LOAD, and FLM signals. Two kinds of data width, 1-
and 4-bit, are supported for most monochrome LCD panels.
Refer to FIGURE 16-2 for both 1- and 4-bit interface timing.
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