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參數資料
| 型號： | ST2202 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 8 BIT Integrated Microcontroller with 256K Bytes ROM |
| 中文描述： | 8位微控制器集成256K字節(jié)ROM的 |
| 文件頁數： | 40/65頁 |
| 文件大?。?/td> | 1946K |
| 代理商： | ST2202 |
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Sitronix
ST2202
Ver 2.0a
40/65
2003-May-05
1
1
6
6
.
.
L
L
C
C
D
D
C
C
O
O
N
N
T
T
R
R
O
O
L
L
L
L
E
E
R
R
(
(
L
L
C
C
D
D
C
C
)
)
The LCD controller (LCDC) provides display data and
specific signals for external LCD drivers to drive the STN
LCD panels. The LCDC fetches display data directly from
internal system memory through one unique memory bus.
The special designed internal bus shares almost none of
the CPU resources to make both fast display data process
and high speed CPU operation possible. The ST2202
builds in 4K bytes SRAM, so the maximum panel size can
be 240x120. The LCDC also supports software grayscale to
rich the display information and the diversity of contents as
well.
LCDCK is for LCDC to generate timings and the pixel clock.
It is from OSCK instead of SYSCK, therefore frame content
retains while SYSCK slows down. Refer to TABLE 11-3 for
frequency settings of LCDCK.
The ST2202 supports 1- and 4-bit data bus for the
compatibility of most popular LCD drivers. The LCD output
signals are shared with Port-L., and are controlled by LCD
power control bit
LPWR
(
LCTL[7]
) and data bus selection
bit
LMOD
(
LCK[4]
). In case of 1-bit mode, PL3~1 of Port-L
can still be used for general purpose.
Note: The LCD signals will be disconnected and
Port-L will output values assigned by
PL
after clearing
LPWR
.
Various functions are also supported to rich the display
information, including virtual screen, panning, scrolling,
contrast control and an alternating signal generator. Control
registers used by LCDC are listed below.
TABLE 16-1 Summary Of LCD Control Registers
Bit 7
Bit 6
Bit 5
SSA[7]
SSA[6]
SSA[5]
SSA[15] SSA[14] SSA[13] SSA[12] SSA[11] SSA[10] SSA[9]
VP[7]
VP[6]
VP[5]
VP[4]
XM[7]
XM[6]
XM[5]
XM[4]
YM[7]
YM[6]
YM[5]
YM[4]
-
-
-
-
LPWR
BLNK
REV
-
-
-
-
LMOD
-
-
FRA[5]
FRA[4]
-
-
-
AC[4]
-
-
LPWM[5] LPWM[4] LPWM[3] LPWM[2] LPWM[1] LPWM[0] - - 00 0000
PL[7]
PL[6]
PL[5]
PL[4]
PL[3]
PCL[7]
PCL[6]
PCL[5]
PCL[4]
PCL[3]
Address
$040
$041
$042
$043
$044
$045
$047
$048
$049
$04A
$04B
$04C
$04E
Name
LSSAL
LSSAH
LVPW
LXMAX
LYMAX
LPAN
LCTR
LCK
LFRA
LAC
LPWM
PL
PCL
R/W
W
W
W
R/W
R/W
R/W
R/W
W
W
R/W
R/W
R/W
W
Bit 4
SSA[4]
Bit 3
SSA[3]
Bit 2
SSA[2]
Bit 1
SSA[1]
Bit 0
SSA[0]
SSA[8]
VP[0]
XM[0]
YM[0]
PAN[0]
-
LCK[0]
FRA[0]
AC[0]
Default
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
- - - - -000
100- - - - -
- - -0 0000
- - 00 0000
- - -0 0000
VP[3]
XM[3]
YM[3]
-
-
LCK[3]
FRA[3]
AC[3]
VP[2]
XM[2]
YM[2]
PAN[2]
-
LCK[2]
FRA[2]
AC[2]
VP[1]
XM[1]
YM[1]
PAN[1]
-
LCK[1]
FRA[1]
AC[1]
PL[2]
PCL[2]
PL[1]
PCL[1]
PL[0]
PCL[0]
1111 1111
0000 0000
16.1 LCD Specific Signals
The following signals are generated by LCDC to connect
the ST2202 and an LCD panel. Two of them are dedicated
output pins, while the rest eight pins are multiplexed with
Port-L.
FLM (PL7)
The LCD frame marker signal indicates the start of a new
display frame. FLM becomes active after the last line pulse
of the frame and remains active until the next line pulse, at
which point it de-asserts and remains inactive until the next
frame.
LOAD (PL6)
The LCD line pulse signal is used to latch a line of shifted
data to the segment drivers’ outputs and is also used to
shift the line enable signal of common driver. All the driver
outputs then control the liquid crystal to form the desired
frame on panel.
AC (PL5)
The LCD alternate signal toggles the polarity of liquid
crystal on the panel. This signal can be programmed to
toggle for a period of 1 to 31 lines or one frame. See
section 16.4.7 for register settings.
CP (PL4)
The LCD shift clock pulse signal is the clock output to which
the output data to the LCD panel is synchronized. Data for
segment drivers is shifted into the internal line buffer at
each falling edge of CP.
LD3~0 (PL3~0)
The LCD data bus lines transfer pixel data to the LCD panel
so that it can be displayed. Two kinds of data busses, 1-
and 4-bit, are supported and are controlled by
LMOD
(
LCK[4]
). In case of 1-bit mode,
LMOD
should be cleared
and the LCDC uses only LD0 to transfer data. LD3~1 can
still be programmed to be normal inputs or outputs. The
output pixel data can be inverted through programming.
Setting
REV
(
LCTR
) will reverse the output data on data
bus.
POFF
(Power control)
The LCD power control signal is used to turn on/off the
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參數描述 |
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