參數(shù)資料
型號(hào)： ST2202
廠商： Electronic Theatre Controls, Inc.
英文描述： 8 BIT Integrated Microcontroller with 256K Bytes ROM
中文描述： 8位微控制器集成256K字節(jié)ROM的
文件頁數(shù)： 26/65頁
文件大小： 1946K
代理商： ST2202
Sitronix
12.2 Base Timer
ST2202
Ver 2.0a
26/65
2003-May-05
The base timer supports one interrupt, which occurs at five
different rates. Applications base on the base timer interrupt
can chose an appropriate interrupt rate from five time bases for
their specific needs. These real-time applications may include
digitizer sampling, keyboard debouncing, or communication
polling. Block diagram of base timer is shown in FIGURE 12-2.
2048 Hz
Counter
256 Hz
Counter
64 Hz
Counter
8 Hz
Counter
2 Hz
Counter
CLK32
Control
Register
Base Timer
Interrupt
FIGURE 12-2 Base Timer Block Diagram
12.2.1 Base Timer Operations
The base timer consists of five sub-counters to produce five
predefined rates. The connections between overflow signals of
these sub-counters and the base timer interrupt are controlled
by respective bit fields of base timer enable register (
BTEN
).
The enabled overflow signals are ORed to generate the base
timer interrupt request. Related bits of base timer status
register (
BTSR
) will show which rates of interrupts should be
12.2.2 Base Timer Control/Status Registers
Summary of base timer control/status registers is shown in TABLE 12-3.
serviced. Write “1” to
BTCLR
(bit 7 of
BTSR)
may clear this
register.
Note: Make sure
BTSR
is cleared after the interrupt
was serviced, so that the request can be set next
time.
TABLE 12-3 Summary Of Base Timer Control Registers
Bit 7
Bit 6
Bit 5
Bit 4
-
-
-
BTEN[4] BTEN[3] BTEN[2] BTEN[1] BTEN[0]
-
-
-
BTSR[4] BTSR[3] BTSR[2] BTSR[1] BTSR[0]
BTCLR
-
-
-
-
IRLCD
IRBT
IRPT
-
IELCD
IEBT
IEPT
Address Name
$020
R/W
R/W
R
W
R/W
R/W
Bit 3
Bit 2
Bit 1
Bit 0
Default
- - -0 0000
- - -0 0000
0- - - - - - -
- 000 0000
- 000 0000
BTEN
$021
BTSR
-
-
-
-
$03C
$03E
IREQ
IENA
IRT1
IET1
IRT0
IET0
IRDAC
IEDAC
IRX
IEX
Base Timer Control Register
TABLE 12-4 Base Timer Control Register (BTEN)
Bit 6
Bit 5
Bit 4
-
-
BTEN[4] BTEN[3] BTEN[2] BTEN[1] BTEN[0]
Bit 3:
BTEN3 :
256 Hz interrupt control bit
Address Name
$020
Bit 0:
BTEN0 :
2 Hz interrupt control bit
0
= Disable 2 Hz interrupt
1 = Enable 2 Hz interrupt
Bit 1:
BTEN1 :
8 Hz interrupt control bit
0
= Disable 8 Hz interrupt
1 = Enable 8 Hz interrupt
Bit 2:
BTEN2 :
64 Hz interrupt control bit
0
= Disable 64 Hz interrupt
1 = Enable 64 Hz interrupt
R/W
R/W
Bit 7
-
Bit 3
Bit 2
Bit 1
Bit 0
Default
- - -0 0000
BTEN
0
= Disable 256 Hz interrupt
1 = Enable 256 Hz interrupt
Bit 4:
BTEN4 :
2048 Hz interrupt control bit
0
= Disable 2048 Hz interrupt
1 = Enable 2048 Hz interrupt
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