參數(shù)資料
型號(hào)： ST2202
廠商： Electronic Theatre Controls, Inc.
英文描述： 8 BIT Integrated Microcontroller with 256K Bytes ROM
中文描述： 8位微控制器集成256K字節(jié)ROM的
文件頁(yè)數(shù)： 20/65頁(yè)
文件大?。?/td> 1946K
代理商： ST2202
Sitronix
ST2202
Ver 2.0a
20/65
2003-May-05
1
1
1
1
.
.
C
C
L
L
O
O
C
C
K
K
G
G
E
E
N
N
E
E
R
R
A
A
T
T
O
O
R
R
The ST2202 has two oscillators OSC and OSCX for both
high and low frequency needed. When oscillator mode
selection pin, XMD, is inputted high level, the high
frequency oscillator OSC adopts only one external resistor
to generate a high frequency clock OSCK which is used by
almost every block in chip. OSC can also change to be a
resonator/crystal oscillator by input low level to XMD.
The low frequency oscillator OSCX needs a 32768Hz
crystal and one capacitor to generator a precise frequency
CLK32 for Base timer, Timer1 and the reference clock of
baud rate generator (BGR).
Other clocks are sourced from either OSCK or CLK32 and
are listed below:
System clock:
SYSCK
LCD controller clock:
LCDCK
PSG and PWM DAC clock:
PSGCK
BGR output clock:
BGRCK
SPI transmission clock:
SPICK
SYSCK
The system clock can be switched between OSCK and
CLK32 by resetting or setting
XSEL
(
SYS[7]
). After
XSEL
is
set (or reset), warm-up cycles will be initiated at the same
time. The original clock is still connected until the end of
warm-up cycles. Clock being used can be reported by
reading
XSEL
back.
Note: Test
XSEL
to confirm SYSCK is switched
over successfully before turning down the
original clock.
There are two options for warm-up cycles: 16 / 256 cycles,
which are controlled by
WSKP
(
SYS[3]
). Usually 16 cycles
are enough for OSC and OSCX.
LCDCK
The LCD controller has one four-bit divider to generate
LCDCK directly from OSCK for pixel clock and other
operations. This divider is controlled by
LCKR[3:0]
and the
data mode selection bit
LMOD
(
LCKR[4]
). Refer to TABLE
11-3 for settings of LCDCK.
PSGCK
PSGCK is the clock used by PSG and PWM DAC. It is
sourced from OSCK to make sure of one right and high
enough base frequency and to keep it unchanged. Bits of
PSGC[6:4]
control the options of PSGCK. Refer to TABLE
11-4 for these options.
BGRCK
The ST2202 equips a baud rate generator (BGR), which is
controlled by BGR control register
BCTR
, locked frequency
selection register
BRS
, and divider control register
BDIV
.
The BGR utilizes digital PLL technique to lock a high
frequency
HIGH
F
around OSCK/2. This high frequency is
further scaled down via an integer divider to a desired
frequency BGRCK. The BGR uses CLK32 as reference
clock for the modulation of OSCK. There are two
modulation modes which can be selected by
BMOD
(
BCTR[1]
). The modulation strength is also controllable by
setting or resetting
BSTR
(
BCTR[2]
).
The relation between locked frequency and
BRS
can be
found in the following equation.
=
32
CLK
F
HIGH
OSCK and
HIGH
F
are close related. Value of
the frequency range of the OSCK applied, which is also the
locking range of BGR, and is given by the following
equation, where
α
is the modulation strength coefficient.
OSCK
1
+
α
Although the locked frequency is limited to be around
OSCK, lower frequency can still be obtained by one 8-bit
integer divider, which is assigned by
BDIV
. Thus BGRCK
can be expressed by Equation9-3.
F
BGRCK
=
BRS
Equation9-1
HIGH
F
limits
1
F
2
F
HIGH
HIGH
≤
≤
α
α
α
Equation9-2
BDIV
HIGH
Equation9-3
The SPI block has one three-bit divider to generate SPICK
directly from OSCK for transmission and other operations.
This divider is controlled by
SCKR[6:4]
. Refer to TABLE
11-7 for settings of SPICK.
SPICK
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