參數(shù)資料
型號： SST89C58RC-40-I-TQJE
廠商： Microchip Technology
文件頁數(shù)： 46/88頁
文件大?。?/td> 0K
描述： IC MCU 8BIT FLASH 40TQFP
標準包裝： 160
系列： FlashFlex®
核心處理器： 8051
芯體尺寸： 8-位
速度： 40MHz
連通性： EBI/EMI，I²C，SMBus，UART/USART
外圍設備： 欠壓檢測/復位，POR，WDT
輸入/輸出數(shù)： 32
程序存儲器容量： 32KB（32K x 8）
程序存儲器類型： 閃存
EEPROM 大?。?/td> 2K x 8
RAM 容量： 1K x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 5.5 V
振蕩器型： 外部
工作溫度： -40°C ~ 85°C
封裝/外殼： 44-TQFP
包裝： 托盤
2011 Silicon Storage Technology, Inc.
DS25100A
12/11
50
FlashFlex MCU
SST89C58RC
Data Sheet
A Microchip Technology Company
Master Receiver Mode
The serial data is received via SDA while SCL supplies the serial clock. The first master-transmitted
byte contains the slave address and the data direction bit. In this READ mode, the data direction bit (R/
W) will be logic ‘1’. Serial data is received from the slave via SDA while SCL outputs the serial clock
from the master. After each byte is received from the slave, an acknowledge bit is transmitted by the
master. START and STOP conditions are output to indicate the beginning and end of a serial transfer.
Slave Receiver Mode
The serial data is output through SDA while SCL supplies the serial clock. The first transmitted byte
contains an address and the data direction bit. In this READ mode, the data direction bit (R/W) will be
logic ‘1’. Serial data is transmitted to the master if the address received matches the slave’s assigned
address or if a general call address is received. After each byte is received, an acknowledge bit is
transmitted. START and STOP conditions are recognized as the beginning and end of a serial transfer.
Slave Transmitter Mode
The serial data is received via SDA while SCL supplies the serial clock. The first transmitted byte con-
tains an address and the data direction bit. In this WRITE operation mode, the data direction bit (R/W)
will be logic ‘0’. Serial data is transmitted to the master if the address received matches the slave’s
assigned address or if a general call address is received. After each byte is received, an acknowledge
bit is transmitted. START and STOP conditions are recognized as the beginning and end of a serial
transfer.
Timeouts
SCL Low Timeout
Use the TOE bit to enable monitoring of the SCL low timeout function. When the TOE is set, the
SMBUS controls the TIMER1 to count during every SCL low period. At every falling-edge of the SCL, a
reload counter pulse is generated to TIMER1. At every rising-edge of the SCL, a count stop pulse is
generated to TIMER1. If the TIMER1’s counter is reloaded and counting, the last count stop pulse will
cause the TIMER1 to generate an interrupt for SCL low timeout.
1 = SCL Low timeout enable
0 = SCL Low timeout disabled
SCL High (SMBus Free) Timeout
According to SMBus specifications, the bus is designated as free if the device holds the SCL and SDA
lines high for more than 10 SMBus bit rate cycles.
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