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參數(shù)資料
| 型號： | SSM2160SZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 10/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CTRLR DGTL VOL/CHAN 24SOIC |
| 產(chǎn)品變化通告： | Product Discontinuance 27/Oct/2011 |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 類型： | 立體聲音量控制 |
| 應(yīng)用： | 解碼器，接收器，環(huán)繞系統(tǒng) |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 24-SOIC W |
| 包裝： | 帶卷 (TR) |
REV. A
SSM2160
–3–
TIMING CHARACTERISTICS
Timing
Symbol
Description
Min
Typ
Max
Unit
tCL
Input Clock Pulsewidth, Low
200
ns
tCH
Input Clock Pulsewidth, High
200
ns
tDS
Data Setup Time
50
ns
tDH
Data Hold Time
75
ns
tCW
Positive CLK Edge to End of Write
100
ns
tWC
Write to Clock Setup Time
50
ns
tLW
End of Load Pulse to Next Write
50
ns
tWL
End of Write to Start of Load
50
ns
tL
Load Pulsewidth
250
ns
tW3
Load Pulsewidth (3-Wire Mode)
250
ns
NOTES
1. An idle HI (CLK-HI) or idle LO (CLK-LO) clock may be used. Data is latched on the negative edge.
2. For SPI or Microwire 3-wire bus operation, tie
LD to WRITE and use WRITE pulse to drive both pins. (This generates an automatic internal load signal.)
3. If an idle HI clock is used, tCW and tWL are measured from the final negative transition to the idle state.
4. The first data byte selects an address (MSB HI), and subsequent MSB LO states set gain/attenuation levels. Refer to the Address/Data Decoding Truth Table.
5. Data must be sent MSB first.
D7
D6
D5
D4
D3
D2
D1
D0
0
1
CLK
DATA
WRITE
LD
t
WL
t
L
t
LW
tDH
t
DS
t
CH
0
1
0
1
0
CLK
DATA
WRITE
LD
t
CL
D7
t
WC
t
CW
MSB
Figure 1. Timing Diagrams
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