參數(shù)資料
型號: SSD1905QT2
廠商: Electronic Theatre Controls, Inc.
英文描述: LCD Graphics Controller CMOS
中文描述: LCD圖形控制器的CMOS
文件頁數(shù): 92/153頁
文件大小: 863K
代理商: SSD1905QT2
SSD1905
Rev 1.3
10/2002
SOLOMON
83
Figure 10-13 :
Generic STN Panel Timing
VT
= Vertical Total
= [(REG[19h]bits1-0,REG[18h]bits7-0)+ 1] lines
= LFRAME Pulse Start Position
= [(REG[27h] bits 1-0, REG[26h] bits 7-0)] x HT + (REG[31h] bits 1-0, REG[30h] bits 7-0) pixels
VPW = LFRAME Pulse Width
= [(REG[24h] bits 2-0) + 1] x HT + (REG[35h] bits 1-0, REG[34h] bits 7-0) – (REG[31h] bits 1-0, REG[30h]
bits 7-0) pixels
VDPS = Vertical Display Period Start Position
= [(REG[1Fh]bits1-0,REG[1Eh]bits7-0)] lines
VDP
= Vertical Display Period
= [(REG[1Dh] bits 1-0, REG[1Ch] bits 7-0) + 1] lines
* The VDP must be a minimum of 2 lines
HT
= Horizontal Total
= [((REG[12h] bits 6-0) + 1) x 8] pixels
HPS
= LLINE Pulse Start Position
= [(REG[23h] bits 1-0, REG[22h] bits 7-0) + 1] pixels
HPW = LLINE Pulse Width
= [(REG[20h] bits 6-0) + 1] pixels
HDPS = Horizontal Display Period Start Position
= [(REG[17h]bits1-0,REG[16h]bits7-0)+ 22] pixels
HDP
= Horizontal Display Period
= [((REG[14h] bits 6-0) + 1) x 8] pixels
The HDP must be a minimum of 32 pixels and can be increased by multiples of 8.
*Panel Type Bits (REG[10h] bits 1-0) = 00b (STN)
*LFRAME Pulse Polarity Bit (REG[24h] bit 7) = 1 (active high)
*LLINE Polarity Bit (REG[20h] bit 7) = 1 (active high).
VPS
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