參數(shù)資料
型號(hào): SSD1905QT2
廠商: Electronic Theatre Controls, Inc.
英文描述: LCD Graphics Controller CMOS
中文描述: LCD圖形控制器的CMOS
文件頁數(shù): 90/153頁
文件大?。?/td> 863K
代理商: SSD1905QT2
SSD1905
Rev 1.3
10/2002
SOLOMON
81
10.4 Display Interface
Figure 10-12 :
Panel Timing Parameters
shows the timing parameters required to drive a flat panel display.
Timing details for each supported panel types are provided in the remainder of this section.
Figure 10-12 :
Panel Timing Parameters
Table 10-14 : Panel Timing Parameter Definition and Register Summary
Symbol
HT
HDP
2
Description
Horizontal Total
Horizontal Display Period
2
Derived From
((REG[12h] bits 6-0) + 1) x 8
((REG[14h] bits 6-0) + 1) x 8
((REG[17h]bits1-0,REG[16h]bits7-0)+
Offset
5
)
(REG[23h] bits 1-0, REG[22h] bits 7-0) + 1
(REG[20h] bits 6-0) + 1
((REG[19h] bits 1-0, REG[18h] bits 7-0) + 1) x HT
((REG[1Dh] bits 1-0, REG[1Ch] bits 7-0) + 1) x HT
(REG[1Fh] bits 1-0, REG[1Eh] bits 7-0) x HT
(REG[27h] bits 1-0, REG[26h] bits 7-0) x HT +
(REG[31h] bits 1-0, REG[30h] bits 7-0)
((REG[24h] bits 2-0) + 1) x HT + (REG[35h] bits 1-
0, REG[34h] bits 7-0) – (REG[31h] bits 1-0,
REG[30h] bits 7-0)
Units
HDPS
3
HPS
HPW
VT
VDP
4
VDPS
VPS
Horizontal Display Period Start Position
3
LLINE Pulse Start Position
LLINE Pulse Width
Vertical Total
Vertical Display Period
4
Vertical Display Period Start Position
LFRAME Pulse Start Position
Ts
1
VPW
LFRAME Pulse Width
Ts
1
HPW
VT
VDPS
HDPS
HDP
HT
HPS
VDP
VPS
VPW
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