參數(shù)資料
型號: SSD1905QT2
廠商: Electronic Theatre Controls, Inc.
英文描述: LCD Graphics Controller CMOS
中文描述: LCD圖形控制器的CMOS
文件頁數(shù): 58/153頁
文件大?。?/td> 863K
代理商: SSD1905QT2
SSD1905
Rev 1.3
10/2002
SOLOMON
49
Table 7-18 : PWM Duty Cycle Select Options
PWM Duty Cycle [7:0]
00h
01h
02h
FFh
PWM Duty Cycle
Always Low
High for 1 out of 256 clock periods
High for 2 out of 256 clock periods
High for 255 out of 256 clock periods.
7.2.10 Cursor Mode Registers
Cursor Feature Register
Bit
7
REG[C0h]
0
6
5
4
3
2
1
Cursor1
Enable
RW
0
Cursor2
Enable
RW
0
0
0
0
0
0
0
Type
Reset
state
Bit 7
NA
0
NA
0
NA
0
NA
0
NA
0
NA
0
Cursor1 Enable
When this bit = 0 Cursor1 is disabled.
When this bit = 1 Cursor1 is enabled.
Cursor2 Enable
When this bit = 0, Cursor2 is disabled.
When this bit = 1, Cursor2 is enabled.
Note
This register is effective for 4/8/16 bpp (REG[70h] Bits 2:0 = 010/011/100)
Bit 6
For Hardware Cursors operation, see Section 20 “Hardware Cursor Mode”.
Cursor1 Blink Total Register 0
7
REG[C4h]
0
Bit
6
5
4
3
2
1
Cursor1
Blink Total
Bit 7
RW
0
Cursor1
Blink Total
Bit 6
RW
0
Cursor1
Blink Total
Bit 5
RW
0
Cursor1
Blink Total
Bit 4
RW
0
Cursor1
Blink Total
Bit 3
RW
0
Cursor1
Blink Total
Bit 2
RW
0
Cursor1
Blink Total
Bit 1
RW
0
Cursor1
Blink Total
Bit 0
RW
0
Type
Reset
state
Cursor1 Blink Total Register 1
7
REG[C5h]
0
Bit
6
5
4
3
2
1
0
0
0
0
0
0
Cursor1
Blink Total
Bit 9
RW
0
Cursor1
Blink Total
Bit 8
RW
0
Type
Reset
state
NA
0
NA
0
NA
0
NA
0
NA
0
NA
0
REG[C5h] bits 1-0,
REG[C4h] bits 7-0
Cursor1 Blink Total Bits [9:0]
This is the total blinking period per frame for cursor1. This register must be set to a
non-zero value in order to make the cursor visible.
Note
These bits will not effective until the Cursor1 Enable bit is set to 1 (REG[C0h] bit 7=1).
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