參數(shù)資料
型號(hào): SSD1905QT2
廠商: Electronic Theatre Controls, Inc.
英文描述: LCD Graphics Controller CMOS
中文描述: LCD圖形控制器的CMOS
文件頁數(shù): 57/153頁
文件大?。?/td> 863K
代理商: SSD1905QT2
SOLOMON
Rev 1.3
10/2002
SSD1905
48
Bits 3-1
CV Pulse Divide Select Bits [2:0]
The value of these bits represents the power of 2 by which the selected CV Pulse
source is divided.
Note
This divided clock is further divided by 2 before it is output at the LCVOUT.
Table 7-17 : CV Pulse Divide Select Options
CV Pulse Divide Select Bits [2:0]
0h
1h
2h
3h
...
7h
CV Pulse Divide Amount
1
2
4
8
...
128
Bit 0
PWMCLK Source Select
When this bit = 0, the clock source for PWMCLK is CLKI.
When this bit = 1, the clock source for PWMCLK is AUXCLK.
Note
For further information on the PWMCLK source select, see Section 11 “Clocks”.
CV Pulse Burst Length Register
7
REG[B2h]
0
Bit
6
5
4
3
2
1
CV Pulse
Burst
Length
Bit 7
RW
0
CV Pulse
Burst
Length
Bit 6
RW
0
CV Pulse
Burst
Length
Bit 5
RW
0
CV Pulse
Burst
Length
Bit 4
RW
0
CV Pulse
Burst
Length
Bit 3
RW
0
CV Pulse
Burst
Length
Bit 2
RW
0
CV Pulse
Burst
Length
Bit 1
RW
0
CV Pulse
Burst
Length
Bit 0
RW
0
Type
Reset
state
Bits 7-0
CV Pulse Burst Length Bits [7:0]
The value of this register determines the number of pulses generated in a single CV
Pulse burst:
Number of pulses in a burst = Bits [7:0] + 1
PWM Duty Cycle Register
7
REG[B3h]
0
Bit
6
5
4
3
2
1
PWM
Duty Cycle
Bit 7
RW
0
PWM
Duty Cycle
Bit 6
RW
0
PWM
Duty Cycle
Bit 5
RW
0
PWM
Duty Cycle
Bit 4
RW
0
PWM
Duty Cycle
Bit 3
RW
0
PWM
Duty Cycle
Bit 2
RW
0
PWM
Duty Cycle
Bit 1
RW
0
PWM
Duty Cycle
Bit 0
RW
0
Type
Reset
state
Bits 7-0
PWM Duty Cycle Bits [7:0]
This register determines the duty cycle of the PWM output.
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