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SSD1905
Rev 1.3
10/2002
SOLOMON
29
Bit 5 is effective for 320x240 HR-TFT panels only (REG[10h] bit 3 = 1, REG[10h] bits 1-0 =
10).
If bit 4 is set to 1, LSHIFT pin will be driven high at power saving mode.
Bits 4-2 are effective for HR-TFT panels only (REG[10h] bits 1-0 = 10).
Bits 1-0 are effective for 160x160 HR-TFT panels only (REG[10h] bit 3 = 0 and REG[10h]
bits 1-0 = 10).
For panel AC timing and timing parameter definitions, see Section 10.4.8 “160x160 Sharp
HR-TFT Panel Timing (e.g. LQ031B1DDxx)” and 10.4.9 “320x240 Sharp HR-TFT Panel
Timing (e.g. LQ039Q2DS01)”.
GPIO0 Pulse Start Register
7
GPIO0
Start Bit 7
Start Bit 6
RW
0
REG[3Ch]
0
GPIO0
Start Bit 0
RW
0
Bit
6
5
4
3
2
1
GPIO0
GPIO0
Start Bit 5
RW
0
GPIO0
Start Bit 4
RW
0
GPIO0
Start Bit 3
RW
0
GPIO0
Start Bit 2
RW
0
GPIO0
Start Bit 1
RW
0
Type
Reset
state
Bits 7-0
RW
0
GPIO0 Pulse Start [7:0]
These bits specify the start offset of the GPIO0 signal within a line, in 1 pixel resolution.
Note
This register is effective for 320x240 HR-TFT panels and GPIO Preset enabled only
(REG[10h] bit 3 = 1, REG[10h] bits 1-0 = 10 and REG[38h] bit 5 = 1).
For panel AC timing and timing parameter definitions, see Section 10.4.9 “320x240 Sharp
HR-TFT Panel Timing (e.g. LQ039Q2DS01)”.
GPIO0 Pulse Stop Register
7
GPIO0 Stop
Bit 7
RW
0
REG[3Eh]
0
GPIO0 Stop
Bit 0
RW
0
Bit
6
5
4
3
2
1
GPIO0 Stop
Bit 6
RW
0
GPIO0 Stop
Bit 5
RW
0
GPIO0 Stop
Bit 4
RW
0
GPIO0 Stop
Bit 3
RW
0
GPIO0 Stop
Bit 2
RW
0
GPIO0 Stop
Bit 1
RW
0
Type
Reset
state
Bits 7-0
GPIO0 Pulse Stop [7:0]
These bits specify the stop offset of the GPIO0 signal within a line, in 1 pixel resolution.
Note
This register is effective for 320x240 HR-TFT panels and GPIO Preset enabled only
(REG[10h] bit 3 = 1, REG[10h] bits 1-0 = 10 and REG[38h] bit 5 = 1).
For panel AC timing and timing parameter definitions, see Section 10.4.9 “320x240 Sharp
HR-TFT Panel Timing (e.g. LQ039Q2DS01)”.