參數(shù)資料
型號： SSD1905QT2
廠商： Electronic Theatre Controls, Inc.
英文描述： LCD Graphics Controller CMOS
中文描述： LCD圖形控制器的CMOS
文件頁數(shù)： 34/153頁
文件大小： 863K
代理商： SSD1905QT2
SSD1905
Rev 1.3
10/2002
SOLOMON
25
Vertical Display Period Start Position Register 0
7
6
Vertical
Display
Period Start
Position Bit
7
6
RW
RW
0
0
REG[1Eh]
0
Vertical
Display
Period Start
Position Bit
0
RW
0
Bit
5
4
3
2
1
Vertical
Display
Period Start
Position Bit
Vertical
Display
Period Start
Position Bit
5
RW
0
Vertical
Display
Period Start
Position Bit
4
RW
0
Vertical
Display
Period Start
Position Bit
3
RW
0
Vertical
Display
Period Start
Position Bit
2
RW
0
Vertical
Display
Period Start
Position Bit
1
RW
0
Type
Reset
state
Vertical Display Period Start Position Register 1
7
6
0
0
REG[1Fh]
0
Vertical
Display
Start
Position
Period Bit 8
RW
0
Bit
5
0
4
0
3
0
2
0
1
Vertical
Display
Start
Position
Period Bit 9
RW
0
Type
Reset
state
REG[1Fh] bits 1-0,
REG[1Eh] bits 7-0
NA
0
NA
0
NA
0
NA
0
NA
0
NA
0
Vertical Display Period Start Position Bits [9:0]
These bits specify the Vertical Display Period Start Position in 1 line resolution.
Note
For panel AC timing and timing parameter definitions, see Section 10.4 “Display
Interface”.
LLINE Pulse Width Register
7
LLINE
Pulse
Polarity
RW
0
REG[20h]
0
LLINE
Pulse Width
Bit 0
RW
0
Bit
6
5
4
3
2
1
LLINE
Pulse Width
Bit 6
RW
0
LLINE
Pulse Width
Bit 5
RW
0
LLINE
Pulse Width
Bit 4
RW
0
LLINE
Pulse Width
Bit 3
RW
0
LLINE
Pulse Width
Bit 2
RW
0
LLINE
Pulse Width
Bit 1
RW
0
Type
Reset
state
Bit 7
LLINE Pulse Polarity
This bit determines the polarity of the horizontal sync signal. The horizontal sync signal
is typically named as LLINE or LP, depending on the panel type.
When this bit = 0, the horizontal sync signal is active low.
When this bit = 1, the horizontal sync signal is active high.
LLINE Pulse Width Bits [6:0]
These bits specify the width of the panel horizontal sync signal, in number of PCLK.
The horizontal sync signal is typically named as LLINE or LP, depending on the panel
type.
LLINE Pulse Width in PCLK = Bits [6:0] + 1
Bits 6-0
Note
For panel AC timing and timing parameter definitions, see Section 10.4 “Display Interface”.
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