參數(shù)資料
型號(hào)： SSD1905QT2
廠商： Electronic Theatre Controls, Inc.
英文描述： LCD Graphics Controller CMOS
中文描述： LCD圖形控制器的CMOS
文件頁數(shù)： 33/153頁
文件大?。?/td> 863K
代理商： SSD1905QT2
SOLOMON
Rev 1.3
10/2002
SSD1905
24
Vertical Total Register 1
7
0
REG[19h]
0
Vertical
Total Bit 8
RW
0
Bit
6
0
5
0
4
0
3
0
2
0
1
Vertical
Total Bit 9
RW
0
Type
Reset
state
REG[19h] bits 1-0,
REG[18h] bits 7-0
NA
0
NA
0
NA
0
NA
0
NA
0
NA
0
Vertical Total Bits [9:0]
These bits specify the LCD panel Vertical Total period, in 1 line resolution. The Vertical
Total is the sum of the Vertical Display Period and the Vertical Non-Display Period.
The maximum Vertical Total is 1024 lines. See Figure 10-12 :
Panel Timing
Parameters
.
Vertical Total in number of lines = Bits [9:0]+ 1
Note
This register must be programmed such that the following condition is fulfilled.
For passive LCD interface : VDPS + VDP + 1 < VT
For other LCD interface : VDPS + VDP < VT
For panel AC timing and timing parameter definitions, see Section 10.4 “Display
Interface”.
Vertical Display Period Register 0
7
Vertical
Display
Period Bit 7
Period Bit 6
RW
RW
0
REG[1Ch]
0
Vertical
Display
Period Bit 0
RW
0
Bit
6
5
4
3
2
1
Vertical
Display
Vertical
Display
Period Bit 5
RW
0
Vertical
Display
Period Bit 4
RW
0
Vertical
Display
Period Bit 3
RW
0
Vertical
Display
Period Bit 2
RW
0
Vertical
Display
Period Bit 1
RW
0
Type
Reset
state
0
Vertical Display Period Register 1
7
0
REG[1Dh]
0
Vertical
Display
Period Bit 8
RW
0
Bit
6
0
5
0
4
0
3
0
2
0
1
Vertical
Display
Period Bit 9
RW
0
Type
Reset
state
REG[1Dh] bits 1-0,
REG[1Ch] bits 7-0
NA
0
NA
0
NA
0
NA
0
NA
0
NA
0
Vertical Display Period Bits [9:0]
These bits specify the LCD panel Vertical Display period, in 1 line resolution. The
Vertical Display period should be less than the Vertical Total to allow for a sufficient
Vertical Non-Display period.
Vertical Display Period in number of lines = Bits [9:0] + 1
Note
For panel AC timing and timing parameter definitions, see Section 10.4 “Display
Interface”.
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