參數(shù)資料
型號： SSD1905QT2
廠商： Electronic Theatre Controls, Inc.
英文描述： LCD Graphics Controller CMOS
中文描述： LCD圖形控制器的CMOS
文件頁數(shù)： 32/153頁
文件大小： 863K
代理商： SSD1905QT2
SSD1905
Rev 1.3
10/2002
SOLOMON
23
Horizontal Display Period Register
7
6
0
Horizontal
Display
Period Bit 6
NA
RW
0
0
REG[14h]
Bit
5
4
3
2
1
0
Horizontal
Display
Period Bit 5
RW
0
Horizontal
Display
Period Bit 4
RW
0
Horizontal
Display
Period Bit 3
RW
0
Horizontal
Display
Period Bit 2
RW
0
Horizontal
Display
Period Bit 1
RW
0
Horizontal
Display
Period Bit 0
RW
0
Type
Reset
state
Bits 6-0
Horizontal Display Period Bits [6:0]
These bits specify the LCD panel Horizontal Display period, in 8 pixel resolution. The
Horizontal Display period should be less than the Horizontal Total to allow for a
sufficient Horizontal Non-Display period.
Horizontal Display Period in number of pixels = (Bits [6:0] + 1) x 8
Note
Maximum value of REG[14h]
≤
0x3F when Display Rotate Mode (90
°
or 270
°
) is
selected.
For panel AC timing and timing parameter definitions, see Section 10.4 “Display
Interface”.
Horizontal Display Period Start Position Register 0
7
6
Horizontal
Display
Period Start
Position Bit
7
6
RW
RW
0
0
REG[16h]
0
Horizontal
Display
Period Start
Position Bit
0
RW
0
Bit
5
4
3
2
1
Horizontal
Display
Period Start
Position Bit
Horizontal
Display
Period Start
Position Bit
5
RW
0
Horizontal
Display
Period Start
Position Bit
4
RW
0
Horizontal
Display
Period Start
Position Bit
3
RW
0
Horizontal
Display
Period Start
Position Bit
2
RW
0
Horizontal
Display
Period Start
Position Bit
1
RW
0
Type
Reset
state
Horizontal Display Period Start Position Register 1
7
6
0
0
REG[17h]
0
Horizontal
Display
Period Start
Position Bit
8
RW
0
Bit
5
0
4
0
3
0
2
0
1
Horizontal
Display
Period Start
Position Bit
9
RW
0
Type
Reset
state
REG[17h] bits1-0,
REG[16h] bits 7-0
NA
0
NA
0
NA
0
NA
0
NA
0
NA
0
Horizontal Display Period Start Position Bits [9:0]
These bits specify the Horizontal Display Period Start Position in 1 pixel resolution.
Note
For panel AC timing and timing parameter definitions, see Section 10.4 “Display
Interface”.
Vertical Total Register 0
7
Vertical
Total Bit 7
RW
0
REG[18h]
0
Vertical
Total Bit 0
RW
0
Bit
6
5
4
3
2
1
Vertical
Total Bit 6
RW
0
Vertical
Total Bit 5
RW
0
Vertical
Total Bit 4
RW
0
Vertical
Total Bit 3
RW
0
Vertical
Total Bit 2
RW
0
Vertical
Total Bit 1
RW
0
Type
Reset
state
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