參數(shù)資料
型號: SSD1905QT2
廠商: Electronic Theatre Controls, Inc.
英文描述: LCD Graphics Controller CMOS
中文描述: LCD圖形控制器的CMOS
文件頁數(shù): 28/153頁
文件大?。?/td> 863K
代理商: SSD1905QT2
SSD1905
Rev 1.3
10/2002
SOLOMON
19
Look-Up Table Write Address Register
7
6
LUT Write
Address Bit
7
6
WO
WO
0
0
REG[0Bh]
0
LUT Write
Address Bit
0
WO
0
Bit
5
4
3
2
1
LUT Write
Address Bit
LUT Write
Address Bit
5
WO
0
LUT Write
Address Bit
4
WO
0
LUT Write
Address Bit
3
WO
0
LUT Write
Address Bit
2
WO
0
LUT Write
Address Bit
1
WO
0
Type
Reset
state
Bits 7-0
LUT Write Address Bits [7:0]
This register is a pointer to the Look-Up Table (LUT) which is used to write LUT data
stored in REG[08h], REG[09h], and REG[0Ah].
The data is updated to the LUT only
with the completion of a write to this register
. This is a write-only register and
returns 00h if read.
Note
The SSD1905 has three 256-entry, 6-bit-wide LUTs, one for each of red, green and
blue (see Section 15 “Look-Up Table Architecture”).
Look-Up Table Blue Read Data Register
7
6
LUT Blue
Read Data
Bit 5
Bit 4
RO
RO
0
0
REG[0Ch]
0
0
Bit
5
4
3
2
1
0
LUT Blue
Read Data
LUT Blue
Read Data
Bit 3
RO
0
LUT Blue
Read Data
Bit 2
RO
0
LUT Blue
Read Data
Bit 1
RO
0
LUT Blue
Read Data
Bit 0
RO
0
Type
Reset
state
Bits 7-2
RO
0
RO
0
LUT Blue Read Data Bits [5:0]
This register contains the data from the blue component of the Look-Up Table. The
LUT entry read is controlled by the LUT Read Address Register (REG[0Fh]).
Note
This register is updated only when the LUT Read Address Register (REG[0Fh]) is
written.
Look-Up Table Green Read Data Register
7
6
LUT Green
Read Data
Bit 5
Bit 4
RO
RO
0
0
REG[0Dh]
0
0
Bit
5
4
3
2
1
0
LUT Green
Read Data
LUT Green
Read Data
Bit 3
RO
0
LUT Green
Read Data
Bit 2
RO
0
LUT Green
Read Data
Bit 1
RO
0
LUT Green
Read Data
Bit 0
RO
0
Type
Reset
state
Bits 7-2
RO
0
RO
0
LUT Green Read Data Bits [5:0]
This register contains the data from the green component of the Look-Up Table. The
LUT entry read is controlled by the LUT Read Address Register (REG[0Fh]).
Note
This register is updated only when the LUT Read Address Register (REG[0Fh]) is
written.
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