參數(shù)資料
型號: SSD1905QT2
廠商: Electronic Theatre Controls, Inc.
英文描述: LCD Graphics Controller CMOS
中文描述: LCD圖形控制器的CMOS
文件頁數(shù): 25/153頁
文件大小: 863K
代理商: SSD1905QT2
SOLOMON
Rev 1.3
10/2002
SSD1905
16
Product / Revision Code Register
7
Product
Code
Bit 5
Bit 4
RO
RO
0
REG[03h]
0
Revision
Code Bit 0
RO
X
Bit
6
5
4
3
2
1
Product
Code
Product
Code
Bit 3
RO
0
Product
Code
Bit 2
RO
1
Product
Code
Bit 1
RO
0
Product
Code
Bit 0
RO
1
Revision
Code Bit 1
RO
X
Type
Reset
state
Bits 7-2
0
Product Code Bits [5:0]
These bits indicate the product code. The product code of SSD1905 is 000101.
Revision Code Bits [1:0]
These are read-only bits that indicate the revision code.
Bits 1-0
7.2.2 Clock Configuration Registers
Memory Clock Configuration Register
Bit
7
0
REG[04h]
6
0
5
4
3
0
2
0
1
0
0
0
MCLK
Divide
Select Bit 1
RW
0
MCLK
Divide
Select Bit 0
RW
0
Type
Reset
state
Bits 5-4
NA
0
NA
0
NA
0
NA
0
NA
0
NA
0
MCLK Divide Select Bits [1:0]
These bits determine the divide used to generate the Memory Clock (MCLK) from the
Bus Clock (BCLK).
Table 7-1 : MCLK Divide Selection
MCLK Divide Select Bits [1:0]
00
01
10
11
BCLK to MCLK Frequency Ratio
1:1
2:1
3:1
4:1
Pixel Clock Configuration Register
7
6
0
PCLK
Divide
Select Bit 2
NA
RW
0
0
REG[05h]
0
PCLK
Source
Select Bit 0
RW
0
Bit
5
4
3
0
2
0
1
PCLK
Divide
Select Bit 1
RW
0
PCLK
Divide
Select Bit 0
RW
0
PCLK
Source
Select Bit 1
RW
0
Type
Reset
state
Bits 6-4
NA
0
NA
0
PCLK Divide Select Bits [2:0]
These bits determine the divided used to generate the Pixel Clock (PCLK) from the
Pixel Clock Source.
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