參數(shù)資料
型號(hào): SSD1905QT2
廠商: Electronic Theatre Controls, Inc.
英文描述: LCD Graphics Controller CMOS
中文描述: LCD圖形控制器的CMOS
文件頁數(shù): 23/153頁
文件大小: 863K
代理商: SSD1905QT2
SOLOMON
Rev 1.3
10/2002
SSD1905
14
MCU Mode (Endian)
MC68EZ328 /
MC68VZ328 (Big)
A0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
RD/WR#
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
RD#
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
WE1#
X
0
0
1
X
0
0
1
1
0
0
1
1
0
0
1
WE0#
X
0
1
0
X
0
1
0
1
0
1
0
1
0
1
0
Operation
Word read
Word write
High byte write 2N
Low byte write 2N+1
Word read
Word write
High byte write 2N+1
Low byte write 2N
Word read
Word write
High byte write 2N
Low byte write 2N+1
Word read
Word write
High byte write 2N+1
Low byte write 2N
MC68EZ328 /
MC68VZ328 (Little)
SH-3/SH-4 (Big)
SH-3/SH-4 (Little)
6
FUNCTIONAL BLOCK DESCRIPTIONS
6.1
Responds to bus request for various kinds of MCU and translates to internal interface signals.
MCU Interface
6.2
The control register stores register data to control the LCD panel. The register data is through the MCU Interface
read/write to control the register value. The read/write access of LUT is also controlled by the control register. The
detail of this register and register mapping will be discussed in Section 7 “Registers”.
Control Register
6.3
Display output serializes the display data from display buffer and reconstructs the data according to the display
panel format. When the display mode is not 16 bpp, display data will be converted to color data by the built-in 18
bit LUT. For details about LUT, please refer to Section 15 “Look-Up Table Architecture”.
Display Output
6.4
Display buffer consists of 80KB SRAM, which is organized as a 32-bit wide internal data path for fast display data
retrieval.
Display Buffer
6.5
Provides programmable waveform for Pulse Width Modulation (PWM) and Contrast Voltage (CV) generation.
PWM Clock and CV Pulse Control
6.6
Clock Generator provides internal clocks. For detail operation of clock generator, please refer to Section 11
“Clocks”.
Clock Generator
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