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SOLOMON
Rev 1.3
10/2002
SSD1905
12
5.8
LCD Interface Pin Mapping
Table 5-8 : LCD Interface Pin Mapping
Pin Name
Monochrome
Passive Panel
Color Passive Panel
Color TFT Panel
4-bit
8-bit
4-bit
8-bit
(format
stripe)
9-bit
12-bit
18-bit
18-bit Sharp
HR-TFT
1
LFRAME
LLINE
LSHIFT
LDEN
LDATA0
LDATA1
LDATA2
LDATA3
LDATA4
LDATA5
LDATA6
LDATA7
LDATA8
LDATA9
LDATA10
LDATA11
LDATA12
LDATA13
LDATA14
LDATA15
LDATA16
LDATA17
GPIO0
GPIO1
GPIO2
GPIO3
LFRAME
LLINE
LSHIFT
SPS
LP
CLK
MOD
LDEN
R3
R2
R1
G3
G2
G1
B3
B2
B1
R0
Drive 0
Drive 0
G0
Drive 0
Drive 0
B0
Drive 0
Drive 0
GPIO0
GPIO1
GPIO2
GPIO3
no connect
R5
R4
R3
G5
G4
G3
B5
B4
B3
R2
R1
R0
G2
G1
G0
B2
B1
B0
PS
CLS
REV
SPL
GPIO4
(output only)
GPIO5
(output only)
GPIO6
(output only)
Drive 0
Drive 0
Drive 0
Drive 0
D0
D1
D2
D3
Drive 0
Drive 0
Drive 0
Drive 0
Drive 0
Drive 0
Drive 0
Drive 0
Drive 0
Drive 0
GPIO0
GPIO1
GPIO2
GPIO3
D0
D1
D2
D3
D4
D5
D6
D7
Drive 0
Drive 0
Drive 0
Drive 0
D0(R2)
2
D1(B1)
2
D2(G1)
2
D3(R1)
2
Drive 0
Drive 0
Drive 0
Drive 0
Drive 0
Drive 0
Drive 0
Drive 0
Drive 0
Drive 0
GPIO0
GPIO1
GPIO2
GPIO3
D0(G3)
2
D1(R3)
2
D2(B2)
2
D3(G2)
2
D4(R2)
2
D5(B1)
2
D6(G1)
2
D7(R1)
2
Drive 0
Drive 0
Drive 0
Drive 0
Drive 0
Drive 0
Drive 0
Drive 0
Drive 0
Drive 0
GPIO0
GPIO1
GPIO2
GPIO3
R2
R1
R0
G2
G1
G0
B2
B1
B0
R5
R4
R3
G5
G4
G3
B5
B4
B3
R2
R1
R0
G2
G1
G0
B2
B1
B0
Drive 0
Drive 0
Drive 0
Drive 0
Drive 0
Drive 0
Drive 0
Drive 0
Drive 0
Drive 0
GPIO0
GPIO1
GPIO2
GPIO3
Drive 0
Drive 0
Drive 0
Drive 0
Drive 0
Drive 0
Drive 0
Drive 0
Drive 0
GPIO0
GPIO1
GPIO2
GPIO3
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO4
GPIO4
GPIO4
GPIO4
GPIO4
GPIO4
GPIO4
GPIO5
GPIO5
GPIO5
GPIO5
GPIO5
GPIO5
GPIO5
GPIO5
GPIO6
GPIO6
GPIO6
GPIO6
GPIO6
GPIO6
GPIO6
GPIO6
GPO
LCVOUT
LPWMOUT
GPO (General Purpose Output)
LCVOUT
LPWMOUT
Note
1
GPIO pins must be configured as outputs (CF3 = 0 during RESET# active) when HR-TFT panels are selected.
2
These pin mappings use signal names commonly used for each panel type, however signal names may differ
between panel manufacturers. The values shown in brackets represent the color components as mapped to the
corresponding LDATAxx signals at the first valid edge of LSHIFT. For further LDATAxx to LCD interface
mapping, see Section 10.4 “Display Interface”.