參數(shù)資料
型號： SSD1905QT2
廠商： Electronic Theatre Controls, Inc.
英文描述： LCD Graphics Controller CMOS
中文描述： LCD圖形控制器的CMOS
文件頁數(shù)： 19/153頁
文件大?。?/td> 863K
代理商： SSD1905QT2
SOLOMON
Rev 1.3
10/2002
SSD1905
10
5.3
Clock Input
Table 5-3 : Clock Input Pin Descriptions
Pin Name
Type
TQFP
Pin #
Cell
RESET#
State
Description
CLKI
I
15
LIS
—
Typically used as input clock source for bus clock and
memory clock
This pin may be used as input clock source for pixel
clock. This input pin must be connected to V
SS
if not
used.
AUXCLK
I
77
LIS
—
5.4
Miscellaneous
Table 5-4 : Miscellaneous Pin Descriptions
Pin Name
Type
TQFP
Pin #
Cell
RESET
# State
Description
CF[7:0]
I
78-85
LIS
—
These inputs are used to configure the SSD1905 – see
Table 5-6 : Summary of Power-On/Reset Options.
Note: These pins are used for configuration of the
SSD1905 and must be connected directly to IOV
DD
or V
SS
.
General Purpose Output (possibly used for controlling
the LCD power).
Test Enable input used for production test only and
should be tied to V
SS
.
GPO
O
47
LO3
0
TESTEN
I
86
LIS
—
5.5
Power and Ground
Table 5-5 : Power And Ground Pin Descriptions
Pin Name
Type
TQFP
Pin #
16, 26,
37, 49,
63, 76
Cell
RESET
# State
Description
IOV
DD
P
P
—
Power supply pins. It is recommended to place a
0.1
μ
F bypass capacitor close to each of these pins.
COREV
DD
P
1, 51
P
—
COREV
DD
pins are internal voltage regulator output
pins that is used by the internal circuitry only. They
cannot be used for driving external circuitry.
It is required to place a 0.1
μ
F bypass capacitor
close to each of these pins.
V
SS
P
14, 25,
36, 50,
62, 75,
100
P
—
Ground pins
5.6
These pins are used for configuration of the SSD1905 and must be connected directly to IOV
DD
or V
SS
. The state
of CF[5:0] is latched on the rising edge of RESET# or after the software reset function is activated (REG[A2h] bit
0). Changing state at any other time has no effect.
Summary of Configuration Options
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