參數(shù)資料
型號: SSD1905QT2
廠商: Electronic Theatre Controls, Inc.
英文描述: LCD Graphics Controller CMOS
中文描述: LCD圖形控制器的CMOS
文件頁數(shù): 131/153頁
文件大?。?/td> 863K
代理商: SSD1905QT2
SOLOMON
Rev 1.3
10/2002
SSD1905
122
Line Address Offset
The Main Window Line Address Offset register (REG[78h], REG[79h]) is based on the display
width and programmed using the following formula.
Main Window Line Address Offset bits 9-0
= Display width in pixels
÷
(32
÷
bpp)
= 160 pixels
÷
(32
÷
8 bpp)
= 40 (28h)
18.2 180° Display Rotate Mode
The following figure shows how the programmer sees a 240x160 landscape image and how the image is
being displayed. The application image is written to the SSD1905 in the following sense: A–B–C–D. The
display is refreshed by the SSD1905 in the following sense: D-C-B-A.
A
B
C
D
Display
Rotate
Window
physical memory
start address
image seen by programmer
= image in display buffer
1
240
240
1
display start address
(panel origin)
image refreshed by SSD1905
D
R
W
A
B
C
D
Figure 18-2 : Relationship Between The Screen Image and the Image Refreshed in 180
°
Display Rotate
Mode.
18.2.1 Register Programming
Enable 180
°
Display Rotate Mode
Set Display Rotate Mode Select bits to 10 (REG[71h] bits 1:0 = 10).
Display Start Address
The display refresh circuitry starts at pixel “D”, therefore the Main Window Display Start Address
registers (REG[74h], REG[75h], REG[76h]) must be programmed with the address of pixel “D”.
To calculate the value of the address of pixel “D” use the following formula (assumes 8bpp color
depth).
Main Window Display Start Address bits 16-0
= ((Image address + (image width x (panel height – 1) + panel width) x bpp
÷
8)
÷
4) –1
= ((0 + (240 pixels x 159 pixels + 240 pixels) x 8 bpp
÷
8)
÷
4) – 1
= 9599 (257Fh)
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