參數(shù)資料
型號: SSD1905QT2
廠商: Electronic Theatre Controls, Inc.
英文描述: LCD Graphics Controller CMOS
中文描述: LCD圖形控制器的CMOS
文件頁數(shù): 127/153頁
文件大?。?/td> 863K
代理商: SSD1905QT2
SOLOMON
Rev 1.3
10/2002
SSD1905
118
15.2.5 16 Bit-Per-Pixel Color Mode
The LUT is bypassed at 16 bpp and the color data is directly mapped for this color depth. The color pixel is
arranged as 5-6-5 RGB format. See Figure 14-1 : 1/2/4/8/16 Bit-Per-Pixel Display Data Memory Organization.
16 Big-Endian Bus Interface
16.1 Byte Swapping Bus Data
The display buffer and register architecture of the SSD1905 is inherently little-endian. If configured as big-
endian (CF4 = 1 at reset), bus accesses are automatically handled by byte swapping all read/write data
to/from the internal display buffer and registers.
Bus data byte swapping translates all byte accesses correctly to the SSD1905 register and display buffer
locations. To maintain the correct translation for 16-bit word access, even address bytes must be mapped
to the MSB of the 16-bit word, and odd address bytes to the LSB of the 16-bit word. For example:
aa
cc
dd
bb
bb
dd
cc
aa
aabb ccdd
MSB
LSB
2
0
2
0
0
15
0
15
Display
Data
Byte Swap
System
Memory
Address
Display
Buffer
Address
D[15:8]
D[7:0]
* MSB is assumed to be associated with even address.
* LSB is assumed to be associated with odd address.
Display
Buffer
(Little-Endian)
System
Memory
(Big-Endian)
CPU Data
Byte Swap
Byte write 11h to register address 1Eh ->
Byte write 22h to register address 1Fh ->
Word write 1122h to register address 1Eh->
REG[1Eh] <= 11h
REG[1Fh] <= 22h
REG[1Eh] <= 11h
REG[1Fh] <= 22h
Figure 16-1 :
Byte-swapping for 16 Bpp
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