參數(shù)資料
型號: SSD1905QT2
廠商: Electronic Theatre Controls, Inc.
英文描述: LCD Graphics Controller CMOS
中文描述: LCD圖形控制器的CMOS
文件頁數(shù): 119/153頁
文件大?。?/td> 863K
代理商: SSD1905QT2
SOLOMON
Rev 1.3
10/2002
SSD1905
110
12 Power Saving Mode
Power Saving Mode is incorporated into the SSD1905 to accommodate the need for power reduction in the hand-
held device market. This mode is enabled via the Power Saving Mode Enable bit (REG[A0h] bit 0).
Power Saving Mode power down the panel and stop display refresh accesses to the display buffer.
Table 12-1 : Power Saving Mode Function Summary
Software Power
Saving
Yes
No
1
Yes
No
No
Forced Low
4
Stopped
Forced Low
Yes
Normal
IO Access Possible
Memory Access Possible
Look-Up Table Registers Access Possible
Sequence Controller Running
Display Active
LCD Interface Outputs
PWMCLK
GPIO3:0 Pins configured for HR-TFT
2
GPIO Pins configured as GPIOs Access Possible
2
Yes
Yes
Yes
Yes
Yes
Active
Active
Active
Yes
Note :
1
When Power Saving mode is enabled, the memory controlled is powered down. The status of the memory
controlled is indicated by the Memory Controller Power Saving Status bit (REG[A0h] bit 3). For Power Saving
Status AC timing, see Section 10.3.3 “Power Saving Status”.
2
GPIO Pins are configured using the configurations pin CF3 which is latched on the rising edge of RESET#. For
information on CF3, see Table 5-6 : Summary of Power-On/Reset Options.
3
GPIOs can be accessed and if configured as outputs can be changed.
4
Except the LCD interface pins LDEN and LSHIFT in STN and CSTN mode.
After reset, the SSD1905 stays in Power Saving Mode. Software must initialize the chip (i.e. programs all registers)
and then clear the Power Saving Mode Enable bit.
13 Frame Rate Calculation
The following formula is used to calculate the display frame rate.
f
FrameRate
=
)
(
)
(
VT
x
HT
PCLK
Where:
f
PCLK
HT
= PCLK frequency (Hz)
= Horizontal Total
= ((REG[12h] bits 6-0) + 1) x 8 Ts
= Vertical Total
= ((REG[19h] bits 1-0, REG[18h] bits 7-0) + 1) Lines
VT
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