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參數(shù)資料
| 型號： | SSD1854U |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | LCD Segment / Common Driver with Controller CMOS |
| 中文描述： | LCD段/與普通的CMOS驅動器控制器 |
| 文件頁數(shù)： | 27/48頁 |
| 文件大?。?/td> | 771K |
| 代理商： | SSD1854U |
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SSD1854
Series
Rev 1.0
08/2002
SOLOMON
22
7.13 Command Table
Table 5 - COMMAND TABLE
Hex
00~0F
Bit Pattern
0000 C
3
C
2
C
1
C
0
Command
Set Lower
Column Address
Set Upper
Column Address
Set Master/Slave
Mode
Reserved
Set Internal
Regulator
Resistor Ratio
Description
Set the lower nibble of the column address pointer for
RAM access. The pointer is reset to 0 after reset.
Set the upper nibble of the column address pointer for
RAM access. The pointer is reset to 0 after reset.
M
0
=0: Master operation mode (POR)
M
0
=1: Slave operation mode
Reserved
The internal regulator gain increases as R
2
R
1
R
0
is
increased from 000b to 111b. The factor, 1+R
2
/R
1
, is
given by:
R
2
R
1
R
0
= 000: 3.2 (POR)
R
2
R
1
R
0
= 001: 3.9
R
2
R
1
R
0
= 010: 4.6
R
2
R
1
R
0
= 011: 5.3
R
2
R
1
R
0
= 100: 6.0
R
2
R
1
R
0
= 101: 6.7
R
2
R
1
R
0
= 110: 7.4
R
2
R
1
R
0
= 111: 8.1
(Refer to section 8.4)
VC=0: turn OFF the internal voltage booster (POR)
VC=1: turn ON the internal voltage booster
VR=0: turn OFF the internal regulator (POR)
VR=1: turn ON the internal regulator
VF=0: turn OFF the output op-amp buffer (POR)
VF=1: turn ON the output op-amp buffer
Reserved
The second command specifies the row address pointer
of the RAM data to be displayed in first row of window.
The value must be within 0 to window row number + 15.
See the RAM Mapping Table for examples.
The second command specifies the mapping of first
display line (COM0) to one of ROW0~159. COM0 is
mapped to ROW0 after reset.
The second command specifies the number of lines to
be displayed. Duties 1/16~1/160 could be selected. The
duty ratio is set to 1/160 after reset. See the Ram
Mapping Table for examples.
The second command sets the n-line inversion register
from 1 to 63 lines to reduce display crosstalk. Register
values from 00001b to 11111b are mapped to 1 line to
63 lines respectively. Value 00000b disables the N-line
inversion.
Sets the LCD bias corresponding to different mux
number.
B
2
B
1
B
0
:
000: 32mux
010: 96mux
100: 128mux
110: 160mux (POR)
Reserved
10~17
0001 0C
6
C
5
C
4
18~19
0001 100M
0
1A~1F
20~27
0010 0R
2
R
1
R
0
28~2F
0010 1VCVRVF
Set Power
Control Register
30~3F
40~43
0100 00XX
L
7
L
6
L
5
L
4
L
3
L
2
L
1
L
0
Reserved
Set Display Start
Line
44~47
0100 01XX
C
7
C
6
C
5
C
4
C
3
C
2
C
1
C
0
Set Display
Offset
48~4B
0100 10XX
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
Set Multiplex
Ratio
4C~4F
0100 11XX
XXN
5
N
4
N
3
N
2
N
1
N
0
Set N-line
Inversion
50~57
0101 0B
2
B
1
B
0
Set LCD Bias
58~5F
Reserved
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