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參數(shù)資料
| 型號(hào)： | SSD1854 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | LCD Segment / Common Driver with Controller CMOS |
| 中文描述： | LCD段/與普通的CMOS驅(qū)動(dòng)器控制器 |
| 文件頁(yè)數(shù)： | 34/48頁(yè) |
| 文件大小： | 771K |
| 代理商： | SSD1854 |
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SSD1854
Series
Rev 1.0
08/2002
SOLOMON
29
For 4 FRC,
Memory Content
1
st
Byte
0
0
1
1
FRAME
2
nd
Byte
0
1
0
1
Gray Mode
1
st
WA
LA
DA
BA
2
nd
WB
LB
DB
BB
3
rd
WC
LC
DC
BC
4
th
WD
LD
DD
BD
White
Light Gray
Dark Gray
Black
For 3 FRC,
Memory Content
1
st
Byte
0
0
1
1
FRAME
2
nd
Byte
0
1
0
1
Gray Mode
1
st
WA
LA
DA
BA
2
nd
WB
LB
DB
BB
3
rd
WC
LC
DC
BC
4
th
(No use)
WD (XX)
LD (XX)
DC (XX)
BC (XX)
White
Light Gray
Dark Gray
Black
8.16 Set Segment Re-map [A0~A1]
This commands changes the mapping between the display data column address and segment
driver. It allows flexibility in layout during LCD module assembly. Refer to
Figure 5.
8.17 Set Entire Display On/Off [A4~A5]
This command forces the entire display to be illuminated regardless of the contents of the
GDDRAM. This command has priority than the “Set Normal/Reverse Display” but lower priority
than the “Set Display On/Off” command.
8.18 Set Normal/Reverse Display [A6~A7]
This command sets the display to be either normal/reverse. In reverse display, a RAM data of
‘0’ indicates an “ON” pixel while in normal display; a RAM data of ‘0’ indicates an “OFF” pixel.
This command has lower priority than both “Set Display On/Off” and “Set Entire Display
On/Off”.
8.19 Set Power Save Mode [A9]
This command is to force the chip to enter Sleep Mode. The internal oscillator and LCD power
supply will be turn off when enter to such mode.
8.20 Start Internal Oscillator [AB]
After POR, the internal oscillator is OFF. It should be turned ON by sending this command to
the chip.
8.21 Set Display On/Off [AE~AF]
This command is used to turn the display on or off, by the value of the LSB. It has the highest
priority over other commands regarding the display effect.
8.22 Set Page Address [B0~BF]
This command positions the page address of 0 to 21 possible positions in GDDRAM. Refer to
Figure 5. During 16-bits write operation, the last bit of the page address is ignored, D0-D7
always writes to even page and D8-D15 always writes to odd address.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SSD1854U | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:LCD Segment / Common Driver with Controller CMOS |
| SSD1854Z | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:LCD Segment / Common Driver with Controller CMOS |
| SSD1858 | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:LCD Segment / Common Driver with Controller CMOS |
| SSD1858Z | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:LCD Segment / Common Driver with Controller CMOS |
| SSD1905 | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:LCD Graphics Controller CMOS |
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