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ii
6.18
V
EXT
..............................................................................................................................................9
6.19
V
L7
,
V
L6
,
V
L5
,
V
L4
,
V
L3
and V
L2
.......................................................................................................9
6.20
COM0 – COM159......................................................................................................................10
6.21
SEG0 – SEG127........................................................................................................................10
6.22
C
AP
,
C
AN
,
C
BP
, C
BN
, C
CP
, C
CN
,
C
DP
, and C
DN
...............................................................................10
6.23
N/C.............................................................................................................................................10
7
FUNCTIONAL BLOCK DESCRIPTIONS ........................................................................................11
7.1
Command Decoder and Command Interface........................................................................11
7.2
MPU Parallel 6800-series Interface ........................................................................................11
7.3
MPU Parallel 8080-series Interface ........................................................................................11
7.4
MPU Serial 4-wire Interface.....................................................................................................12
7.5
MPU Serial 3-wire interface.....................................................................................................12
7.6
Graphic Display Data RAM (GDDRAM)..................................................................................12
7.7
Oscillator Circuit......................................................................................................................12
7.8
LCD Driving Voltage Generator and Regulator ....................................................................13
7.9
288 Bit Latch ............................................................................................................................13
7.10
Level selector...........................................................................................................................14
7.11
HV Buffer Cell (Level Shifter)..................................................................................................14
7.12
Default Setting after Reset......................................................................................................15
7.13
Command Table.......................................................................................................................22
7.14
Read Status Byte .....................................................................................................................25
7.15
Data Read / Write .....................................................................................................................25
8
COMMAND DESCRIPTIONS ..........................................................................................................26
8.1
Set Lower Column Address [00~0F]......................................................................................26
8.2
Set Higher Column Address [10~17] ....................................................................................26
8.3
Set Master/Slave Mode [18~19]..............................................................................................26
8.4
Set Internal Regulator Resistors Ratio [20~27]....................................................................26