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參數(shù)資料
| 型號(hào)： | SSD1852Z |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | LCD Segment / Common Driver With Controller CMOS |
| 中文描述： | LCD段/與普通的CMOS驅(qū)動(dòng)器控制器 |
| 文件頁數(shù)： | 28/55頁 |
| 文件大?。?/td> | 637K |
| 代理商： | SSD1852Z |
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SSD1852
Rev 1.0
01/2003
SOLOMON
23
Bit Pattern
1000 0011
Command
OTP programming
Description
This command start program LCD driver with OTP offset
value. This command only execute once. No effect on the
second run. Detail of OTP programming procedure on
page 30.
This command enable /disable the Direct Memory Access
mode .
This command set the start column address (A
6
~A
0
), end
column address (C
6
~C
0
), start page address (B
3
~B
0
) and
end page address (D
3
~D
0
) in DMA mode. The page and
column address should be follow the below rule.
Min. value Max value
A
6
~A
0
0000000 C
6
~C
0
B
3
~B
0
0000 D
3
~D
0
C
6
~C
0
A
6
~A
0
1111111
D
3
~D
0
B
3
~B
0
1111
Remarks: this command is available only when DMA mode
is enabled.
X
0
= 0 : Lock the IC. The driver ignores all command and
data written, except the unlock command or pin reset.
X
0
= 1 : Unlock the IC. The driver accepts any command
and data written.
1111 0100
0000 0X
0
10
1000 0100
0A
6
A
5
A
4
A
3
A
2
A
1
A
0
0000 B
3
B
2
B
1
B
0
0C
6
C
5
C
4
C
3
C
2
C
1
C
0
0000 D
3
D
2
D
1
D
0
Enable DMA mode
Set Start/End Column
and Page address in
DMA mode
1111 1101
0001 0X
0
10
Lock / Unlock
Interface
Read Status Byte
(
D/C
= 0,
R/
W
(
WR
)
= 1,
E(
RD
)
= 1)
An 8 bits status byte will be placed onto the data bus when a read operation is performed if D/C is low. The status
byte is defined as follows:
Bit Pattern
Command
BUSY ON RES MF
2
MF
1
MF
0
DS
1
DS
0
Description
BUSY
0: Chip is idle
1: Chip is executing instruction
ON
0: Display is OFF
1: Display is ON
RES
0: Chip is idle
1: Chip is executing reset
MF
2
- MF
0
: 010
DS
1
, DS
0
: Display size
Read Display Status
Data Read / Write
(
D/C
= 1,
R/
W
(
WR
)
= 1,
E(
RD
)
= 1)
To read data from the GDDRAM, input High to R/
W
(
WR
) pin and D/C pin for 6800-series parallel mode,
Low to E(
RD
) pin and High to D/C pin for 8080-series parallel mode. No data read is provided for serial mode. In
normal mode, GDDRAM column address pointer will be increased by one automatically after each data read. Also, a
dummy read is required before the first data is read. See
Figure 3
in Functional Description.
To write data to the GDDRAM, input Low to R/
W
(
WR
) pin and High to D/C pin for 6800-series parallel mode. For
serial interface, it will always be in write mode. GDDRAM column address pointer will be increased by one
automatically after each data write. The address will be reset to 0 in execution of next data read/write operation when
it is 127.
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